1 //==========================================================================
3 // devs_eth_arm_board.inl
5 // Board ethernet I/O definitions.
7 //==========================================================================
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40 //===========================================================================
42 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHR
43 #include <cyg/hal/hal_if.h>
46 #include <pkgconf/redboot.h>
47 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
49 #include <flash_config.h>
53 extern unsigned int sys_ver;
57 #ifdef CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
59 #if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
60 RedBoot_config_option("Set " CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME " network hardware address [MAC]",
65 RedBoot_config_option(CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME " network hardware address [MAC]",
70 RedBoot_config_option("Set FEC network hardware address [MAC]",
75 RedBoot_config_option("FEC network hardware address [MAC]",
80 #endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
82 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
83 // Note that this section *is* active in an application, outside RedBoot,
84 // where the above section is not included.
86 #include <cyg/hal/hal_if.h>
89 #define CONFIG_ESA (6)
92 #define CONFIG_BOOL (1)
95 cyg_bool _board_provide_eth0_esa(struct cs8900a_priv_data* cpd)
99 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
100 "eth0_esa", &set_esa, CONFIG_BOOL);
102 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
103 "eth0_esa_data", cpd->esa, CONFIG_ESA);
106 return ok && set_esa;
109 void _board_provide_fec_esa(void)
115 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
116 "fec_esa", &set_esa, CONFIG_BOOL);
117 diag_printf("Ethernet FEC MAC address: ");
119 CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
120 "fec_esa_data", addr, CONFIG_ESA);
121 //diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
122 // addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
123 if(sys_ver == SOC_SILICONID_Rev1_0) {
124 writel(addr[5], SOC_FEC_MAC_BASE + 0x0);
125 writel(addr[4], SOC_FEC_MAC_BASE + 0x4);
126 writel(addr[3], SOC_FEC_MAC_BASE + 0x8);
127 writel(addr[2], SOC_FEC_MAC_BASE + 0xC);
128 writel(addr[1], SOC_FEC_MAC_BASE + 0x10);
129 writel(addr[0], SOC_FEC_MAC_BASE + 0x14);
130 addr[5] = readl(SOC_FEC_MAC_BASE + 0x0);
131 addr[4] = readl(SOC_FEC_MAC_BASE + 0x4);
132 addr[3] = readl(SOC_FEC_MAC_BASE + 0x8);
133 addr[2] = readl(SOC_FEC_MAC_BASE + 0xC);
134 addr[1] = readl(SOC_FEC_MAC_BASE + 0x10);
135 addr[0] = readl(SOC_FEC_MAC_BASE + 0x14);
137 writel(addr[5], SOC_FEC_MAC_BASE2 + 0x0);
138 writel(addr[4], SOC_FEC_MAC_BASE2 + 0x4);
139 writel(addr[3], SOC_FEC_MAC_BASE2 + 0x8);
140 writel(addr[2], SOC_FEC_MAC_BASE2 + 0xC);
141 writel(addr[1], SOC_FEC_MAC_BASE2 + 0x10);
142 writel(addr[0], SOC_FEC_MAC_BASE2 + 0x14);
143 addr[5] = readl(SOC_FEC_MAC_BASE2 + 0x0);
144 addr[4] = readl(SOC_FEC_MAC_BASE2 + 0x4);
145 addr[3] = readl(SOC_FEC_MAC_BASE2 + 0x8);
146 addr[2] = readl(SOC_FEC_MAC_BASE2 + 0xC);
147 addr[1] = readl(SOC_FEC_MAC_BASE2 + 0x10);
148 addr[0] = readl(SOC_FEC_MAC_BASE2 + 0x14);
150 diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
151 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
153 diag_printf("is not set\n");
157 RedBoot_init(_board_provide_fec_esa, RedBoot_INIT_LAST);
158 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
161 // ------------------------------------------------------------------------
162 // EEPROM access functions
164 #define PP_ECR 0x0040
165 #define PP_EE_READ_CMD 0x0200
166 #define PP_EE_WRITE_CMD 0x0100
167 #define PP_EE_EWEN_CMD 0x00F0
168 #define PP_EE_EWDS_CMD 0x0000
169 #define PP_EE_ERASE_CMD 0x0300
171 #define PP_EE_DATA 0x0042
172 #define PP_EE_ADDR_W0 0x001C
173 #define PP_EE_ADDR_W1 0x001D
174 #define PP_EE_ADDR_W2 0x001E
176 #define EE_TIMEOUT 50000
177 __inline__ cyg_uint16 read_eeprom(cyg_addrword_t base, cyg_uint16 offset)
179 unsigned long timeout = EE_TIMEOUT;
180 if (get_reg(base, PP_SelfStat) & PP_SelfStat_EEPROM) {
182 diag_printf("EEPROM PP_SelfStat=0x%x\n", get_reg(base, PP_SelfStat));
185 diag_printf("Error: NO EEPROM present\n");
189 while ((timeout -- > 0) && (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY))
192 diag_printf("read_eeprom() timeout\n");
195 timeout = EE_TIMEOUT;
196 put_reg(base, PP_ECR, (offset | PP_EE_READ_CMD));
197 while ((timeout -- > 0) && (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY))
200 diag_printf("read_eeprom() timeout\n");
203 return get_reg(base, PP_EE_DATA);
207 * Write a word to an EEPROM location
208 * base: package page base (IO base)
209 * offset: the EEPROM word offset starting from 0. So for word 1, should pass in 1
210 * data: 16 bit data to be written into EEPRM
212 __inline__ void write_eeprom(cyg_addrword_t base, cyg_uint16 offset, cyg_uint16 data)
214 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
216 put_reg(base, PP_ECR, PP_EE_EWEN_CMD);
217 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
219 put_reg(base, PP_ECR, PP_EE_ERASE_CMD|offset);
220 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
222 put_reg(base, PP_EE_DATA, data);
223 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
225 put_reg(base, PP_ECR, (PP_EE_WRITE_CMD|offset));
226 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
228 put_reg(base, PP_ECR, PP_EE_EWDS_CMD);
229 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
233 #define CS8900A_RESET_BYPASS /* define it when reset is done early */
235 static __inline__ void copy_eeprom(cyg_addrword_t base)
239 for (i = 0; i < 6; i += 2) {
240 esa_word = read_eeprom(base, PP_EE_ADDR_W0 + (i/2));
241 put_reg(base, (PP_IA+i), esa_word);
242 // diag_printf("base=0x%x, copy_eeprom (0x%04x)\n", base, esa_word);
246 #undef CYGHWR_CL_CS8900A_PLF_RESET
247 #define CYGHWR_CL_CS8900A_PLF_RESET(base) copy_eeprom(base)
249 static cs8900a_priv_data_t cs8900a_eth0_priv_data = {
250 base : (cyg_addrword_t) BOARD_CS_LAN_BASE,
251 interrupt: CYGNUM_HAL_INTERRUPT_ETH,
252 #ifdef CYGSEM_DEVS_ETH_ARM_MXCBOARD_ETH0_SET_ESA
253 esa : CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_ESA,
254 hardwired_esa : true,
256 hardwired_esa : false,
258 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
259 provide_esa : &_board_provide_eth0_esa,
265 ETH_DRV_SC(cs8900a_sc,
266 &cs8900a_eth0_priv_data, // Driver specific data
267 CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME,
274 cs8900a_deliver, // "pseudoDSR" called from fast net thread
275 cs8900a_poll, // poll function, encapsulates ISR and DSR
278 NETDEVTAB_ENTRY(cs8900a_netdev,
279 "cs8900a_" CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME,
283 #endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
285 #endif // __WANT_DEVS