1 //==========================================================================
3 // devs/eth/arm/npwr/include/devs_eth_arm_npwr.inl
5 // NPWR ethernet I/O definitions.
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
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31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
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35 // this file might be covered by the GNU General Public License.
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39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //==========================================================================
42 //#####DESCRIPTIONBEGIN####
45 // Contributors:msalter, gthomas
47 // Purpose: NPWR ethernet defintions
48 //####DESCRIPTIONEND####
49 //==========================================================================
51 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHERNET
52 #include <cyg/hal/hal_cache.h> // HAL_DCACHE_LINE_SIZE
53 #include <cyg/hal/hal_io.h> // CYGARC_UNCACHED_ADDRESS
55 #ifdef CYGPKG_DEVS_ETH_ARM_NPWR_I82544_ETH0
57 // Use auto speed detection
58 #define CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
60 #define CYGHWR_INTEL_I82544_PCI_VIRT_TO_BUS( _x_ ) ((cyg_uint32)CYGARC_VIRT_TO_BUS(_x_))
61 #define CYGHWR_INTEL_I82544_PCI_BUS_TO_VIRT( _x_ ) ((cyg_uint32)CYGARC_BUS_TO_VIRT(_x_))
63 #define MAX_PACKET_SIZE 1536
64 #define SIZEOF_DESCRIPTOR 16
66 #define CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE \
67 (((MAX_PACKET_SIZE + SIZEOF_DESCRIPTOR) * \
68 (MAX_TX_DESCRIPTORS + MAX_RX_DESCRIPTORS)) + 64)
70 static char pci_mem_buffer[CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE + HAL_DCACHE_LINE_SIZE];
72 #define CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE \
73 (CYGARC_UNCACHED_ADDRESS(((unsigned)pci_mem_buffer + HAL_DCACHE_LINE_SIZE - 1) & ~(HAL_DCACHE_LINE_SIZE - 1)))
75 static I82544 i82544_eth0_priv_data = {
76 #ifdef CYGSEM_DEVS_ETH_ARM_NPWR_I82544_ETH0_SET_ESA
78 mac_address: CYGDAT_DEVS_ETH_ARM_NPWR_I82544_ETH0_ESA
84 ETH_DRV_SC(i82544_sc0,
85 &i82544_eth0_priv_data, // Driver specific data
86 CYGDAT_DEVS_ETH_ARM_NPWR_I82544_ETH0_NAME, // Name for device
98 NETDEVTAB_ENTRY(i82544_netdev0,
99 "i82544_" CYGDAT_DEVS_ETH_ARM_NPWR_I82544_ETH0_NAME,
103 #endif // CYGPKG_DEVS_ETH_ARM_NPWR_I82544_ETH0
106 // These arrays are used for sanity checking of pointers
108 i82544_priv_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
109 #ifdef CYGPKG_DEVS_ETH_ARM_NPWR_I82544_ETH0
110 &i82544_eth0_priv_data,
114 #ifdef CYGDBG_USE_ASSERTS
115 // These are only used when assertions are enabled
116 cyg_netdevtab_entry_t *
117 i82544_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
118 #ifdef CYGPKG_DEVS_ETH_ARM_NPWR_I82544_ETH0
124 i82544_sc_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
125 #ifdef CYGPKG_DEVS_ETH_ARM_NPWR_I82544_ETH0
129 #endif // CYGDBG_USE_ASSERTS
131 // EOF devs_eth_arm_npwr.inl