1 #ifndef CYGONCE_DEVS_ADDERII_ETH_INL
2 #define CYGONCE_DEVS_ADDERII_ETH_INL
3 //==========================================================================
7 // Hardware specifics for A&M AdderII ethernet support
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2002, 2003 Gary Thomas
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //==========================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: gthomas,F.Robbins
52 //####DESCRIPTIONEND####
54 //==========================================================================
57 extern int _adder_get_leds(void);
58 extern void _adder_set_leds(int);
60 #define _get_led() _adder_get_leds()
61 #define _set_led(v) _adder_set_leds(v)
63 #define LED_TxACTIVE 1
64 #define LED_RxACTIVE 2
65 #define LED_IntACTIVE 3
67 // Interrupt generated by device
68 #define FEC_ETH_INT CYGNUM_HAL_INTERRUPT_SIU_LVL1
69 // Address of PHY (transceiver) device
72 // Reset the PHY - analagous to hardware reset
73 #define FEC_ETH_RESET_PHY() \
74 eppc->pip_pbdat &= ~0x00010000; /* Reset PHY chip pb15 */ \
75 CYGACC_CALL_IF_DELAY_US(10000); /* 10ms */ \
76 eppc->pip_pbdat |= 0x00010000; /* Enable PHY chip pb15 */
78 #endif // CYGONCE_DEVS_ADDERII_ETH_INL
79 // ------------------------------------------------------------------------