1 #ifndef CYGONCE_ARM_INTEGRATOR_SERIAL_H
2 #define CYGONCE_ARM_INTEGRATOR_SERIAL_H
4 // ====================================================================
8 // Device I/O - Description of ARM INTEGRATOR serial hardware
10 // ====================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 // ====================================================================
44 //#####DESCRIPTIONBEGIN####
46 // Author(s): David A Rusling
47 // Contributors: Philippe Robin
48 // Date: November 7, 2000
49 // Purpose: Internal interfaces for serial I/O drivers
52 //####DESCRIPTIONEND####
54 // ====================================================================
56 // Description of serial ports on ARM INTEGRATOR7T
59 unsigned char _byte[32];
62 // Little-endian version
63 #if (CYG_BYTEORDER == CYG_LSBFIRST)
65 #define reg(n) _byte[n*4]
67 #else // Big-endian version
69 #define reg(n) _byte[(n*4)^3]
73 /* -------------------------------------------------------------------------------
74 * From AMBA UART (PL010) Block Specification (ARM-0001-CUST-DSPC-A03)
75 * -------------------------------------------------------------------------------
76 * UART Register Offsets.
79 #define AMBA_UARTDR 0x00 /* Data read or written from the interface. */
80 #define AMBA_UARTRSR 0x04 /* Receive status register (Read). */
81 #define AMBA_UARTECR 0x04 /* Error clear register (Write). */
82 #define AMBA_UARTLCR_H 0x08 /* Line control register, high byte. */
83 #define AMBA_UARTLCR_M 0x0C /* Line control register, middle byte. */
84 #define AMBA_UARTLCR_L 0x10 /* Line control register, low byte. */
85 #define AMBA_UARTCR 0x14 /* Control register. */
86 #define AMBA_UARTFR 0x18 /* Flag register (Read only). */
87 #define AMBA_UARTIIR 0x1C /* Interrupt indentification register (Read). */
88 #define AMBA_UARTICR 0x1C /* Interrupt clear register (Write). */
89 #define AMBA_UARTILPR 0x20 /* IrDA low power counter register. */
91 #define AMBA_UARTRSR_OE 0x08
92 #define AMBA_UARTRSR_BE 0x04
93 #define AMBA_UARTRSR_PE 0x02
94 #define AMBA_UARTRSR_FE 0x01
96 #define AMBA_UARTFR_TXFF 0x20
97 #define AMBA_UARTFR_RXFE 0x10
98 #define AMBA_UARTFR_BUSY 0x08
99 #define AMBA_UARTFR_TMSK (AMBA_UARTFR_TXFF + AMBA_UARTFR_BUSY)
101 #define AMBA_UARTCR_RTIE 0x40
102 #define AMBA_UARTCR_TIE 0x20
103 #define AMBA_UARTCR_RIE 0x10
104 #define AMBA_UARTCR_MSIE 0x08
105 #define AMBA_UARTCR_IIRLP 0x04
106 #define AMBA_UARTCR_SIREN 0x02
107 #define AMBA_UARTCR_UARTEN 0x01
109 #define AMBA_UARTLCR_H_WLEN_8 0x60
110 #define AMBA_UARTLCR_H_WLEN_7 0x40
111 #define AMBA_UARTLCR_H_WLEN_6 0x20
112 #define AMBA_UARTLCR_H_WLEN_5 0x00
113 #define AMBA_UARTLCR_H_FEN 0x10
114 #define AMBA_UARTLCR_H_STP2 0x08
115 #define AMBA_UARTLCR_H_EPS 0x04
116 #define AMBA_UARTLCR_H_PEN 0x02
117 #define AMBA_UARTLCR_H_BRK 0x01
119 #define AMBA_UARTIIR_RTIS 0x08
120 #define AMBA_UARTIIR_TIS 0x04
121 #define AMBA_UARTIIR_RIS 0x02
122 #define AMBA_UARTIIR_MIS 0x01
124 #define ARM_BAUD_460800 1
125 #define ARM_BAUD_230400 3
126 #define ARM_BAUD_115200 7
127 #define ARM_BAUD_57600 15
128 #define ARM_BAUD_38400 23
129 #define ARM_BAUD_19200 47
130 #define ARM_BAUD_14400 63
131 #define ARM_BAUD_9600 95
132 #define ARM_BAUD_4800 191
133 #define ARM_BAUD_2400 383
134 #define ARM_BAUD_1200 767
136 // Interrupt Enable Register
142 // Line Control Register
143 #define LCR_WL5 0x00 // Word length
148 #define LCR_SB1 0x00 // Number of stop bits
149 #define LCR_SB1_5 0x00 // 1.5 -> only valid with 5 bit words
152 #define LCR_PN 0x00 // Parity mode - none
153 #define LCR_PE 0x06 // Parity mode - even
154 #define LCR_PO 0x02 // Parity mode - odd
155 #define LCR_PM 0x00 // Forced "mark" parity
156 #define LCR_PS 0x00 // Forced "space" parity
158 // Line Status Register
162 // Modem Control Register
165 #define MCR_INT 0x08 // Enable interrupts
167 static unsigned short select_baud[] = {
177 ARM_BAUD_1200, // 1200
179 ARM_BAUD_2400, // 2400
181 ARM_BAUD_4800, // 4800
183 ARM_BAUD_9600, // 9600
184 ARM_BAUD_14400, // 14400
185 ARM_BAUD_19200, // 19200
186 ARM_BAUD_38400, // 38400
187 ARM_BAUD_57600, // 57600
188 ARM_BAUD_115200, // 115200
189 ARM_BAUD_230400, // 230400
192 static unsigned char select_word_length[] = {
193 LCR_WL5, // 5 bits / word (char)
199 static unsigned char select_stop_bits[] = {
201 LCR_SB1, // 1 stop bit
202 LCR_SB1_5, // 1.5 stop bit
203 LCR_SB2 // 2 stop bits
206 static unsigned char select_parity[] = {
208 LCR_PE, // Even parity
209 LCR_PO, // Odd parity
210 LCR_PM, // Mark parity
211 LCR_PS, // Space parity
214 #endif // CYGONCE_ARM_INTEGRATOR_SERIAL_H