1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: gthomas
49 // Purpose: ARM/AEB-1 platform specific support routines
51 // Usage: #include <cyg/hal/hal_platform_setup.h>
53 //####DESCRIPTIONEND####
55 //===========================================================================*/
57 // From <cyg/hal/hal_cache.h> Need to make that file assembly safe.
58 #define CYG_DEVICE_CCR 0xFFFFA400
59 #define CCR_I 0x08 // Invalidate mode
61 #if CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE==4096
62 // Override default to a more sensible value
63 #undef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
64 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048
67 #ifdef CYGHWR_HAL_ARM_AEB_REVISION_C
68 // AEB rev C has 256kB of memory. Cache is working (set cachable)
69 #define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00048000,0x00007c04
70 #define AEB_BAD .long 0xFFFFA00C,0x00048000,0x01000000,0x00000000
71 #define AEB_CACHE .long 0xFFFFA010,0x60000000,0x61000000,0x00007801
73 // AEB rev B has 128kB of memory. Cache is broken (clear cachable)
74 #define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00028000,0x00007804
75 #define AEB_BAD .long 0xFFFFA00C,0x00028000,0x01000000,0x00000000
76 #define AEB_CACHE .long 0xFFFFA010,0x60000000,0x61000000,0x00007801
79 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
80 #define PLATFORM_SETUP1 \
81 ldr r1,=CYG_DEVICE_CCR ;\
83 strb r2,[r1,#0] /* invalidate... */ ;\
85 strb r2,[r1,#0] /* and disable the cache. */ ;\
86 ldr r1,=segment_register_setups ;\
87 10: ldr r2,[r1,#0] /* segment address */ ;\
90 ldr r3,[r1,#4] /* segment start */ ;\
92 ldr r3,[r1,#8] /* segment end */ ;\
94 ldr r3,[r1,#12] /* segment flags */ ;\
96 add r1,r1,#16 /* next segment */ ;\
98 segment_register_setups: ;\
99 AEB_SRAM /* segment 2 */ ;\
100 AEB_BAD /* segment 3 */ ;\
101 AEB_CACHE /* segment 1 */ ;\
105 #define PLATFORM_SETUP1
108 /*---------------------------------------------------------------------------*/
109 /* end of hal_platform_setup.h */
110 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */