1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
3 //=============================================================================
5 // hal_platform_setup.h
7 // Platform specific support for HAL (assembly code)
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
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41 //####ECOSGPLCOPYRIGHTEND####
42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): Patrick Doyle <wpd@delcomsys.com>
46 // Contributors: Patrick Doyle <wpd@delcomsys.com>
48 // Purpose: Innovator platform specific support routines
50 // Usage: #include <cyg/hal/hal_platform_setup.h>
51 // Only used by "vectors.S"
53 //####DESCRIPTIONEND####
55 //=============================================================================
57 #include <pkgconf/system.h> // System-wide configuration info
58 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
59 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
60 #include CYGHWR_MEMORY_LAYOUT_H
61 #include <cyg/hal/hal_mmu.h> // MMU definitions
62 #include <cyg/hal/innovator.h> // Platform specific hardware definitions
66 #if defined(CYG_HAL_STARTUP_ROM)
67 #define PLATFORM_SETUP1 _platform_setup1
68 #define CYGHWR_HAL_ARM_HAS_MMU
69 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
71 // This is a trick. If the first two words of SRAM are 0x12345678 and
72 // 0x87654321, then, then the reset routine in FLASH branches to the
73 // third location in SRAM. This allows us to test startup code (which may
74 // be broken) without writing it to FLASH and rendering the board useless.
75 // (Well, not permanently useless. Just useless until we track down an
76 // emulator and reload a working copy of RedBoot.) The nifty thing with
77 // the innovator is that, if you press and hold the reset button for
78 // 2 seconds it triggers a power-on-reset. The contents of the internal
79 // SRAM are maintained across such a reset. Thus, we can write our
80 // new test version of RedBoot to SRAM (configured with CYGPRI_HAL_ROM_MLT
81 // set to SRAM) (more on that later), press and hold the reset button,
82 // and see if the new startup code works.
84 // Now for some notes about this
85 // 1) I am guessing about the "2 seconds" part. If you press and hold
86 // the reset button long enough, the FPGA triggers a power-on-reset.
88 // 2) In order to test the SRAM version of RedBoot, import the
89 // redboot_SRAM.ecm file (instead of redboot_RAM.ecm or redboot_ROM.ecm)
90 // and build RedBoot. If you already have RedBoot in FLASH, you can
91 // use that to load redboot.bin with a base address of 0x20000000.
92 // You will be prompted with a "Gee, I don't think 0x20000000 is
93 // a valid address in RAM, are you sure you want to do this?" message.
94 // You should answer "Yes". Here is the command I use:
96 // RedBoot> load -v -r -b 0x20000000 redboot.bin
98 // You can also use the "sloader" application (loaded via
99 // Code Composer Studio) to to load the S-Record file for the SRAM
100 // version of RedBoot.
102 // 3) I may have seen a case where the code tested fine in SRAM, but didn't
103 // work when I placed it in FLASH. But other things could have been
106 #ifdef CYGPRI_HAL_ROM_MLT_SRAM
107 #define PLATFORM_PREAMBLE _platform_preamble
108 .macro _platform_preamble
115 #if defined(DEBUG) && !defined(CYGPRI_HAL_ROM_MLT_SRAM)
116 // Don't enable these macro when we are executing from SRAM because
117 // they overwrite SRAM.
119 #define FAKE_LED_MACRO_SETUP \
120 ldr r0,=0x20000000; \
122 subs r2,r1,#0x20000000; \
123 movlo r1,#0x20000000; \
124 ldr r4,=0x2002fff8; \
126 movhi r1,#0x20000000; \
131 #define FAKE_LED_MACRO(n) \
132 ldr r11,=0x20000000; \
137 #define FAKE_LED_MACRO_SETUP
138 #define FAKE_LED_MACRO(n)
141 // This macro represents the initial startup code for the platform
142 .macro _platform_setup1
143 // See if we should branch to an application stored in
144 // internal SRAM. We do this by checking for a magic cookie
145 // in the first two locations of SRAM and jumping to the
146 // third location in SRAM if we find it (after zeroing those
147 // two locations so we don't create an infinite reboot loop).
163 //#define PLATFORM_SETUP_FROM_CCS_GEL_SCRIPT
164 #ifdef PLATFORM_SETUP_FROM_CCS_GEL_SCRIPT
165 // This is the version of _platform_setup adapted from the contents
166 // of the GEL script shipped with Code Composer Studio
168 // This is all stolen from the ipaq setup
170 // Make sure MMU is OFF
171 mov r0,#INTERNAL_SRAM_BASE // Force cache writeback by reloading
172 add r2,r0,#0x2000 // cache from the internal memory bank
177 mov r1,#0x0070 // MMU Control System bit
178 mcr p15,0,r0,c7,c7,0 // Flush data and instruction cache
179 mcr p15,0,r0,c8,c7,0 // Flush ID TLBs
180 mcr p15,0,r0,c9,c0,0 // Flush Read-Buffer
181 mcr p15,0,r0,c7,c10,4 // Drain write buffer
182 mcr p15,0,r0,c13,c0,0 // Disable virtual ID mapping
183 mcr p15,0,r1,c1,c0,0 // Write MMU control register
186 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
189 // The rest of this is stolen from "init.c" in the sloader program.
190 // FIXME -- add configury
193 // IOB = 1 Initialize on break 1
195 // PLL_MULT = 5 60 MHz clock 0010 1
196 // PLL_DIV = 00: CLKOUT = CLKREF 00
197 // PLL_ENABLE = 1 Enable DPLL 1
198 // BYPASS_DIV = 00: CLKOUT = CLKREF 00
201 // 0x2290: 0010 0010 1001 0000
206 str r2,[r1,#_DPLL_CTL_REG]
208 1: ldr r2,[r1,#_DPLL_CTL_REG]
214 /* Configure ARM9 Memory Interface */
215 /* Set up CS0 for memory & bus size of 16 bits, asynchronous read,
216 * 3 wait states, and a divide by 2 clock.
217 * Set up CS1, CS2, & CS3 the same way, except with 1 wait state.
220 TC_EMIFS_CS0_CONFIG = 0x00003339;
221 TC_EMIFS_CS1_CONFIG = 0x00001139;
222 TC_EMIFS_CS2_CONFIG = 0x00001139;
223 TC_EMIFS_CS3_CONFIG = 0x00001139;
234 /* Configure the SDRAM */
235 /* EMIFF (nCS4) configuration */
236 /* TC_EMIFF_SDRAM_CONFIG = 0x000100F4; */
237 /* MRS (nCS4) initialization */
238 /* TC_EMIFF_MRS = 0x00000037; */
244 /* Disable ARM9 Watchdog Timer by writing the special sequence to it */
246 WATCHDOG_TIMER_MODE = 0x00F5;
247 WATCHDOG_TIMER_MODE = 0x00A0;
249 ldr r1,=WATCHDOG_BASE
254 /* Select the 12MHz oscillator for the frequency reference for the
255 * internal timers. I am doing this today (12/19/02) to simplify my
256 * life -- This way, I don't care what the clock rate of the core is.
259 ldrh r2,[r1,#0x00] // ARM_CKCTL
260 bic r2,r2,#0x1000 // Set ARM_TIMXO = 0
263 /* Enable the MPUXOR_CK by:
264 * "MPUXOR_CK ... is derived from CK_REF ... and is enabled by EN_XORPCK"
266 * EN_XORPCK is bit 1 of ARM_IDLECT2
269 CLKM_ARM_IDLECT2 |= 0x0002;
272 orr r2,r2,#0x0082 // Bits 7 (EN_TIMCK) and 1 (EN_XORPCK)
275 /* Then set the PER_EN bit to 1
277 * PER_EN is bit 0 of ARM_RSTCT2
280 CLKM_ARM_RSTCT2 |= 0x0001;
286 /* Set the "BT_UART_GATING" bit to 1 in the FUNC_MUX_CTRL_0 register.
287 * This enables the TX1 and RTS1 pins.
290 CONFIG_FUNC_MUX_CTRL_0 |= BIT_25;
298 /* Set bit 6 of the FPGA Power Control Register. If I could find some
299 * documentation on this, I could explain better why I am doing this, but
300 * for now, emperical evidence suggests that this disables the "shutdown"
301 * signal to the RS232 level shifter.
304 FPGA_PWR_CTRL_REG |= BIT_06;
309 #ifdef ADD_COMPATIBILITY_FOR_THE_EVM_SOMEDAY
314 // Set up a stack [for calling C code]
315 #if defined(CYG_HAL_STARTUP_SLOADER) || defined(CYG_HAL_STARTUP_ROM)
316 // The startup stack is in internal SRAM
317 ldr sp,=__startup_stack
318 // This _MOST_DEFINATELY_ needs to be fixed
319 orr sp,sp,#0x10000000
321 // The startup stack is in SDRAM, at some virtual address, but
322 // we have not set up the MMU yet, so we need to initialize SP
323 // with the physical address of '__startup_stack'
330 ldr r1,=MMU_Control_Init|MMU_Control_M
331 mcr MMU_CP,0,r1,MMU_Control,c0
334 // mcr MMU_CP,0,r0,MMU_InvalidateCache,c7,0 // Flush data and instruction cache
335 // mcr MMU_CP,0,r0,MMU_TLB,c7,0 // Flush ID TLBs
344 mrc MMU_CP,0,r1,MMU_Control,c0
346 mrc p15,0,r1,c15,c1,0
352 #else // PLATFORM_SETUP_FROM_CCS_GEL_SCRIPT
353 // This is all stolen from the ipaq setup
355 // Make sure MMU is OFF
356 mov r0,#INTERNAL_SRAM_BASE // Force cache writeback by reloading
357 add r2,r0,#0x2000 // cache from the internal memory bank
362 mov r1,#0x0070 // MMU Control System bit
363 mcr p15,0,r0,c7,c7,0 // Flush data and instruction cache
364 mcr p15,0,r0,c8,c7,0 // Flush ID TLBs
365 mcr p15,0,r0,c9,c0,0 // Flush Read-Buffer
366 mcr p15,0,r0,c7,c10,4 // Drain write buffer
367 mcr p15,0,r0,c13,c0,0 // Disable virtual ID mapping
368 mcr p15,0,r1,c1,c0,0 // Write MMU control register
372 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
376 // This is the platform setup adapted from the rrload setup implied
377 // by head_omap1510.S
379 // Disable the Watchdog Timer.
380 // ---------------------------
382 ldr r0, REG_WDT_TIMER_MODE
383 strh r1, [r0] // Set WDTIM Mode
385 strh r1, [r0] // Set WDTIM Mode
388 // setting for DPLL1 control register.
389 // ----------------------------------
390 ldr r0, REG_DPLL1_CTL
393 // Continue to loop if bit shows "not locked"
400 // Init Arm9 processor.
401 // --------------------
402 mrs r0, cpsr // Get current mode bits.
403 bic r0, r0, #0x1f // Clear mode bits.
404 orr r0, r0, #0xd3 // Disable IRQs/FIQs, supervisor mode.
405 msr cpsr, r0 // Enter Supervisor mode.
406 mov r1, #0x81 // Set ARM925T configuration.
407 mcr p15, 0, r1, c15, c1, 0 // Write ARM925T configuration register.
410 // Disable All Interrupts
419 // Determine if this is a 1509 or 1510, then
420 // set the Configuration Registers accordingly
421 // 1509 shows 0, 1510 shows 0x1b47002f
422 // -------------------
429 // OK, so we're a 1510.
432 Errata for ES1 says to do this:
434 1) Check for power-on or warm reset.
435 2) Configure SDRAM controller depending on reset type.
437 // Check for reset type
438 ldr r0, REG_ARM_SYSST
446 // Wait 100mS for SDRAM to stabilize before
447 // configuring SDRAM controller.
448 // Number guessed at.
454 b after_initial_configure_SDRAM
459 // Set auto-refresh counter value to 1.
460 // Program MRS to appropriate CAS latency
461 // Wait for SDRAM array to be completely
462 // refreshed, 1 cycle * #SDRAM rows.
463 ldr r0, REG_TC_EMIFF_SDRAM_CONFIG
466 ldr r0, REG_TC_EMIFF_MRS
467 ldr r1, VAL_TC_EMIFF_MRS
472 ldr r0, REG_TC_EMIFF_SDRAM_CONFIG
476 after_initial_configure_SDRAM:
480 // Config Spec says to write values
481 // to each of the configuration registers,
482 // then take the chip out of 1509 compatibility mode.
484 ldr r0, REG_PULL_DWN_CTRL_0
485 ldr r1, VAL_PULL_DWN_CTRL_0
487 ldr r0, REG_PULL_DWN_CTRL_1
488 ldr r1, VAL_PULL_DWN_CTRL_1
490 ldr r0, REG_PULL_DWN_CTRL_2
491 ldr r1, VAL_PULL_DWN_CTRL_2
493 ldr r0, REG_PULL_DWN_CTRL_3
494 ldr r1, VAL_PULL_DWN_CTRL_3
496 ldr r0, REG_FUNC_MUX_CTRL_4
497 ldr r1, VAL_FUNC_MUX_CTRL_4
499 ldr r0, REG_FUNC_MUX_CTRL_5
500 ldr r1, VAL_FUNC_MUX_CTRL_5
502 ldr r0, REG_FUNC_MUX_CTRL_6
503 ldr r1, VAL_FUNC_MUX_CTRL_6
505 ldr r0, REG_FUNC_MUX_CTRL_7
506 ldr r1, VAL_FUNC_MUX_CTRL_7
508 ldr r0, REG_FUNC_MUX_CTRL_8
509 ldr r1, VAL_FUNC_MUX_CTRL_8
511 ldr r0, REG_FUNC_MUX_CTRL_9
512 ldr r1, VAL_FUNC_MUX_CTRL_9
514 ldr r0, REG_FUNC_MUX_CTRL_A
515 ldr r1, VAL_FUNC_MUX_CTRL_A
517 ldr r0, REG_FUNC_MUX_CTRL_B
518 ldr r1, VAL_FUNC_MUX_CTRL_B
520 ldr r0, REG_FUNC_MUX_CTRL_C
521 ldr r1, VAL_FUNC_MUX_CTRL_C
523 ldr r0, REG_FUNC_MUX_CTRL_D
524 ldr r1, VAL_FUNC_MUX_CTRL_D
526 ldr r0, REG_VOLTAGE_CTRL_0
527 ldr r1, VAL_VOLTAGE_CTRL_0
529 ldr r0, REG_TEST_DBG_CTRL_0
530 ldr r1, VAL_TEST_DBG_CTRL_0
532 ldr r0, REG_MOD_CONF_CTRL_0
533 ldr r1, VAL_MOD_CONF_CTRL_0
537 // Take out of compatibility mode
538 ldr r0, REG_COMP_MODE_CTRL_0
539 ldr r1, VAL_COMP_MODE_CTRL_0
543 b post_config_registers
546 ldr r0, REG_FUNC_MUX_CTRL_0
548 orr r1, r1, #0x6000000 // UART_GIGA_GATE bit as well as UART_BT_GATE bit
550 // Errata for ES5.5 says this must be done before DSP or MPU can
551 // access internal RAMs. This is benign for earlier revs.
552 ldr r0, REG_FUNC_MUX_CTRL_1
556 post_config_registers:
568 mcr p15, 0x0, r0, c7, c5, 0x0
577 mrc p15, 0x0, r1, c1, c0, 0x0
580 mcr p15, 0x0, r1, c1, c0, 0x0
587 // Initialize Traffic Controller (TC)
588 // ----------------------------------
589 ldr r0, REG_TC_IMIF_PRIO
592 ldr r0, REG_TC_EMIFS_PRIO
594 ldr r0, REG_TC_EMIFF_PRIO
597 ldr r0, REG_TC_EMIFS_CONFIG
599 bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */
600 bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */
601 str r1, [r0] // EMIFS GlB Configuration. (value 0x12 most likely)
603 // Set TC chip select registers
604 // SDRAM value based on 168MHz 1510.
605 // ----------------------------
606 ldr r0, REG_TC_EMIFS_CS1_CONFIG
607 ldr r1, VAL_TC_EMIFS_CS1_CONFIG_PRELIM
609 ldr r0, REG_TC_EMIFS_CS2_CONFIG
610 ldr r1, VAL_TC_EMIFS_CS2_CONFIG_PRELIM
612 ldr r0, REG_TC_EMIFF_SDRAM_CONFIG
613 ldr r1, VAL_TC_EMIFF_SDRAM_CONFIG
615 ldr r0, REG_TC_EMIFF_MRS
616 ldr r1, VAL_TC_EMIFF_MRS
625 // Next, Enable the RS232 Line Drivers in the FPGA.
626 // Also, power on the audio CODEC's amplifier here,
627 // which will make a noise on the audio output.
628 // This is done here instead of in the kernel so there
629 // isn't a loud popping noise at the start of each
631 // Also, disable the CODEC's clocks.
632 // omap1510-HelenP1 [specific]
633 ldr r0, REG_FPGA_POWER
635 ldr r2, REG_FPGA_DIP_SWITCH
638 movne r1, #0x62 // Enable the RS232 Line Drivers in the EPLD
640 ldr r0, REG_FPGA_AUDIO
641 mov r1, #0x0 // Disable sound driver (CODEC clocks)
654 str r1, [r0] // yep, that's really a write to address 0x00000000.
656 // *revisit-skranz* is needed?
666 ldr r0, REG_LB_CLOCK_DIV
669 // *revisit-skranz* is needed?
676 // ARM Clock Module Setup
677 // ----------------------
679 ldr r0, REG_ARM_IDLECT2
680 strh r1, [r0] // CLKM, Clock domain control.
682 mov r1, #0x01 // PER_EN bit
683 ldr r0, REG_ARM_RSTCT2
684 strh r1, [r0] // CLKM; Peripheral reset.
688 mov r1, #0x06 // Needed for UART[12]
690 mov r1, #0x86 // Needed for UART[12]
692 ldr r0, REG_ARM_IDLECT2
693 strh r1, [r0] // CLKM, Clock domain control.
695 // Set CLKM to Sync-Scalable
696 mov r1, #0x1000 // Needed for UART[12]
697 ldr r0, REG_ARM_SYSST
700 // *revisit-skranz* is needed?
707 ldr r1, VAL_ARM_CKCTL
708 ldr r0, REG_ARM_CKCTL
711 // setup DPLL1 Control Register
712 // ----------------------------
713 ldr r1, VAL_DPLL1_CTL
714 ldr r0, REG_DPLL1_CTL
716 ands r1, r1, #0x10 // Check if PLL is enabled.
717 beq finish2 // Do not look for lock if BYPASS selected
720 ands r1, r1, #0x01 // Check the LOCK bit.
721 beq poll2 // ...loop until bit goes hi.
725 // Setup TC EMIFS configuration.
726 // CS0 value based on 168MHz
727 // ---------------------------------------------------
728 ldr r1, VAL_TC_EMIFS_CS0_CONFIG // increase flash speed.
729 ldr r0, REG_TC_EMIFS_CS0_CONFIG
730 str r1, [r0] // Chip Select 0
731 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
732 ldr r0, REG_TC_EMIFS_CS1_CONFIG
733 str r1, [r0] // Chip Select 1
734 ldr r1, VAL_TC_EMIFS_CS2_CONFIG
735 ldr r0, REG_TC_EMIFS_CS2_CONFIG
736 str r1, [r0] // Chip Select 2
737 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
738 ldr r0, REG_TC_EMIFS_CS3_CONFIG
739 str r1, [r0] // Chip Select 3
741 // *revisit-skranz* is needed?
748 // The following was added by WPD
749 // Set up a stack [for calling C code]
750 #ifdef CYG_HAL_STARTUP_ROM
751 // The startup stack is in internal SRAM
752 ldr sp,=__startup_stack
753 // This _MOST_DEFINATELY_ needs to be fixed
754 orr sp,sp,#0x10000000
756 // The startup stack is in SDRAM, at some virtual address, but
757 // we have not set up the MMU yet, so we need to initialize SP
758 // with the physical address of '__startup_stack'
766 ldr r1,=MMU_Control_Init|MMU_Control_M
767 mcr MMU_CP,0,r1,MMU_Control,c0
770 // mcr MMU_CP,0,r0,MMU_InvalidateCache,c7,0 // Flush data and instruction cache
771 // mcr MMU_CP,0,r0,MMU_TLB,c7,0 // Flush ID TLBs
781 mrc MMU_CP,0,r1,MMU_Control,c0
783 mrc p15,0,r1,c15,c1,0
792 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_REDBOOT)
793 #define PLATFORM_SETUP1
796 //-----------------------------------------------------------------------------
797 //-----------------------------------------------------------------------------
798 // end of hal_platform_setup.h
800 // ------------------------------------------------------
801 // --------------Static Data Definitions-----------------
802 // ------------------------------------------------------
804 /* inernal OMAP registers */
805 /* interrupt handler level 2 registers */
806 REG_IHL2_MIR: /* 32 bits */
808 /* OMAP configuration registers */
809 REG_FUNC_MUX_CTRL_0: /* 32 bits */
811 REG_FUNC_MUX_CTRL_1: /* 32 bits */
813 REG_FUNC_MUX_CTRL_2: /* 32 bits */
815 REG_COMP_MODE_CTRL_0: /* 32 bits */
817 REG_FUNC_MUX_CTRL_3: /* 32 bits */
819 REG_FUNC_MUX_CTRL_4: /* 32 bits */
821 REG_FUNC_MUX_CTRL_5: /* 32 bits */
823 REG_FUNC_MUX_CTRL_6: /* 32 bits */
825 REG_FUNC_MUX_CTRL_7: /* 32 bits */
827 REG_FUNC_MUX_CTRL_8: /* 32 bits */
829 REG_FUNC_MUX_CTRL_9: /* 32 bits */
831 REG_FUNC_MUX_CTRL_A: /* 32 bits */
833 REG_FUNC_MUX_CTRL_B: /* 32 bits */
835 REG_FUNC_MUX_CTRL_C: /* 32 bits */
837 REG_FUNC_MUX_CTRL_D: /* 32 bits */
839 REG_PULL_DWN_CTRL_0: /* 32 bits */
841 REG_PULL_DWN_CTRL_1: /* 32 bits */
843 REG_PULL_DWN_CTRL_2: /* 32 bits */
845 REG_PULL_DWN_CTRL_3: /* 32 bits */
847 REG_VOLTAGE_CTRL_0: /* 32 bits */
849 REG_TEST_DBG_CTRL_0: /* 32 bits */
851 REG_MOD_CONF_CTRL_0: /* 32 bits */
853 /* local bus control registers */
854 REG_LB_CLOCK_DIV: /* 32 bits */
856 /* watchdog timer registers */
857 REG_WDT_TIMER_MODE: /* 16 bits */
859 /* interrupt handler level 1 registers */
860 REG_IHL1_MIR: /* 32 bits */
862 /* traffic controller memory interface registers */
863 REG_TC_IMIF_PRIO: /* 32 bits */
865 REG_TC_EMIFS_PRIO: /* 32 bits */
867 REG_TC_EMIFF_PRIO: /* 32 bits */
869 REG_TC_EMIFS_CONFIG: /* 32 bits */
871 REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
873 REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
875 REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
877 REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
879 REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */
881 REG_TC_EMIFF_MRS: /* 32 bits */
883 /* MPU clock/reset/power mode control registers */
884 REG_ARM_CKCTL: /* 16 bits */
886 REG_ARM_IDLECT2: /* 16 bits */
888 REG_ARM_RSTCT2: /* 16 bits */
890 REG_ARM_SYSST: /* 16 bits */
892 /* DPLL control registers */
893 REG_DPLL1_CTL: /* 16 bits */
895 /* identification code register */
896 REG_IDCODE: /* 32 bits */
899 /* board-specific registers */
901 REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */
903 REG_FPGA_POWER: /* 8 bits */
905 REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */
907 REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */
912 VAL_COMP_MODE_CTRL_0:
945 /* The OMAP5910 TRM says this register must be 0, but HelenConfRegs
946 * says to write a 7. Don't know what the right thing is to do, so
947 * I'm leaving it at 7 since that's what was already here.
960 VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
962 VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
964 VAL_TC_EMIFS_CS0_CONFIG:
966 VAL_TC_EMIFS_CS1_CONFIG:
968 VAL_TC_EMIFS_CS2_CONFIG:
970 VAL_TC_EMIFS_CS3_CONFIG:
972 VAL_TC_EMIFF_SDRAM_CONFIG:
982 #endif // CYGONCE_HAL_PLATFORM_SETUP_H