1 #ifndef CYGONCE_HAL_VAR_IO_H
2 #define CYGONCE_HAL_VAR_IO_H
3 //=============================================================================
7 // Variant specific registers
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
15 // Copyright (C) 2005, 2006 Andrew Lunn (andrew.lunn@ascom.ch>
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
38 // this file might be covered by the GNU General Public License.
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //=============================================================================
42 //#####DESCRIPTIONBEGIN####
45 // Contributors:jskov, gthomas, tkoeller, tdrury, nickg, asl, John Eigelaar
47 // Purpose: AT91 variant specific registers
49 // Usage: #include <cyg/hal/var_io.h>
51 //####DESCRIPTIONEND####
53 //=============================================================================
55 #include <cyg/hal/plf_io.h>
57 //=============================================================================
61 #define AT91_USART0 0xFFFD0000
65 #define AT91_USART1 0xFFFCC000
68 #define AT91_US_CR 0x00 // Control register
69 #define AT91_US_CR_RxRESET (1<<2)
70 #define AT91_US_CR_TxRESET (1<<3)
71 #define AT91_US_CR_RxENAB (1<<4)
72 #define AT91_US_CR_RxDISAB (1<<5)
73 #define AT91_US_CR_TxENAB (1<<6)
74 #define AT91_US_CR_TxDISAB (1<<7)
75 #define AT91_US_CR_RSTATUS (1<<8)
76 #define AT91_US_CR_STTTO (1<<11)
77 #define AT91_US_MR 0x04 // Mode register
78 #define AT91_US_MR_CLOCK 4
79 #define AT91_US_MR_CLOCK_MCK (0<<AT91_US_MR_CLOCK)
80 #define AT91_US_MR_CLOCK_MCK8 (1<<AT91_US_MR_CLOCK)
81 #define AT91_US_MR_CLOCK_SCK (2<<AT91_US_MR_CLOCK)
82 #define AT91_US_MR_LENGTH 6
83 #define AT91_US_MR_LENGTH_5 (0<<AT91_US_MR_LENGTH)
84 #define AT91_US_MR_LENGTH_6 (1<<AT91_US_MR_LENGTH)
85 #define AT91_US_MR_LENGTH_7 (2<<AT91_US_MR_LENGTH)
86 #define AT91_US_MR_LENGTH_8 (3<<AT91_US_MR_LENGTH)
87 #define AT91_US_MR_SYNC 8
88 #define AT91_US_MR_SYNC_ASYNC (0<<AT91_US_MR_SYNC)
89 #define AT91_US_MR_SYNC_SYNC (1<<AT91_US_MR_SYNC)
90 #define AT91_US_MR_PARITY 9
91 #define AT91_US_MR_PARITY_EVEN (0<<AT91_US_MR_PARITY)
92 #define AT91_US_MR_PARITY_ODD (1<<AT91_US_MR_PARITY)
93 #define AT91_US_MR_PARITY_SPACE (2<<AT91_US_MR_PARITY)
94 #define AT91_US_MR_PARITY_MARK (3<<AT91_US_MR_PARITY)
95 #define AT91_US_MR_PARITY_NONE (4<<AT91_US_MR_PARITY)
96 #define AT91_US_MR_PARITY_MULTI (6<<AT91_US_MR_PARITY)
97 #define AT91_US_MR_STOP 12
98 #define AT91_US_MR_STOP_1 (0<<AT91_US_MR_STOP)
99 #define AT91_US_MR_STOP_1_5 (1<<AT91_US_MR_STOP)
100 #define AT91_US_MR_STOP_2 (2<<AT91_US_MR_STOP)
101 #define AT91_US_MR_MODE 14
102 #define AT91_US_MR_MODE_NORMAL (0<<AT91_US_MR_MODE)
103 #define AT91_US_MR_MODE_ECHO (1<<AT91_US_MR_MODE)
104 #define AT91_US_MR_MODE_LOCAL (2<<AT91_US_MR_MODE)
105 #define AT91_US_MR_MODE_REMOTE (3<<AT91_US_MR_MODE)
106 #define AT91_US_MR_MODE9 17
107 #define AT91_US_MR_CLKO 18
108 #define AT91_US_IER 0x08 // Interrupt enable register
109 #define AT91_US_IER_RxRDY (1<<0) // Receive data ready
110 #define AT91_US_IER_TxRDY (1<<1) // Transmitter ready
111 #define AT91_US_IER_RxBRK (1<<2) // Break received
112 #define AT91_US_IER_ENDRX (1<<3) // Rx end
113 #define AT91_US_IER_ENDTX (1<<4) // Tx end
114 #define AT91_US_IER_OVRE (1<<5) // Rx overflow
115 #define AT91_US_IER_FRAME (1<<6) // Rx framing error
116 #define AT91_US_IER_PARITY (1<<7) // Rx parity
117 #define AT91_US_IER_TIMEOUT (1<<8) // Rx timeout
118 #define AT91_US_IER_TxEMPTY (1<<9) // Tx empty
119 #define AT91_US_IDR 0x0C // Interrupt disable register
120 #define AT91_US_IMR 0x10 // Interrupt mask register
121 #define AT91_US_CSR 0x14 // Channel status register
122 #define AT91_US_CSR_RxRDY 0x01 // Receive data ready
123 #define AT91_US_CSR_TxRDY 0x02 // Transmit ready
124 #define AT91_US_CSR_RXBRK 0x04 // Transmit ready
125 #define AT91_US_CSR_ENDRX 0x08 // Transmit ready
126 #define AT91_US_CSR_ENDTX 0x10 // Transmit ready
127 #define AT91_US_CSR_OVRE 0x20 // Overrun error
128 #define AT91_US_CSR_FRAME 0x40 // Framing error
129 #define AT91_US_CSR_TIMEOUT 0x80 // Timeout
130 #define AT91_US_RHR 0x18 // Receive holding register
131 #define AT91_US_THR 0x1C // Transmit holding register
132 #define AT91_US_BRG 0x20 // Baud rate generator
133 #define AT91_US_RTO 0x24 // Receive time out
134 #define AT91_US_TTG 0x28 // Transmit timer guard
136 // PDC US registers may have different addresses in at91 targets (i.e jtst)
138 #define AT91_US_RPR 0x30 // Receive pointer register
142 #define AT91_US_RCR 0x34 // Receive counter register
146 #define AT91_US_TPR 0x38 // Transmit pointer register
150 #define AT91_US_TCR 0x3c // Transmit counter register
153 // PDC Control register bits
154 #define AT91_US_PTCR_RXTEN (1 << 0)
155 #define AT91_US_PTCR_RXTDIS (1 << 1)
156 #define AT91_US_PTCR_TXTEN (1 << 8)
157 #define AT91_US_PTCR_TXTDIS (1 << 9)
159 // macro could be different from target to target (i.e jtst)
161 #define AT91_US_BAUD(baud) ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(8*(baud))+1)/2)
163 //=============================================================================
167 #define AT91_PIO 0xFFFF0000
170 #define AT91_PIN(_ctrl_, _periph_, _pin_) \
171 ((_ctrl_ << 16) | (_periph_ << 8) | (_pin_))
173 #define AT91_PIO_PER 0x00 // PIO enable
174 #define AT91_PIO_PDR 0x04 // PIO disable
175 #define AT91_PIO_PSR 0x08 // PIO status
177 // GPIO pins on PIO A.
178 #define AT91_GPIO_PA0 AT91_PIN(0,0, 0)
179 #define AT91_GPIO_PA1 AT91_PIN(0,0, 1)
180 #define AT91_GPIO_PA2 AT91_PIN(0,0, 2)
181 #define AT91_GPIO_PA3 AT91_PIN(0,0, 3)
182 #define AT91_GPIO_PA4 AT91_PIN(0,0, 4)
183 #define AT91_GPIO_PA5 AT91_PIN(0,0, 5)
184 #define AT91_GPIO_PA6 AT91_PIN(0,0, 6)
185 #define AT91_GPIO_PA7 AT91_PIN(0,0, 7)
186 #define AT91_GPIO_PA8 AT91_PIN(0,0, 8)
187 #define AT91_GPIO_PA9 AT91_PIN(0,0, 9)
188 #define AT91_GPIO_PA10 AT91_PIN(0,0,10)
189 #define AT91_GPIO_PA11 AT91_PIN(0,0,11)
190 #define AT91_GPIO_PA12 AT91_PIN(0,0,12)
191 #define AT91_GPIO_PA13 AT91_PIN(0,0,13)
192 #define AT91_GPIO_PA14 AT91_PIN(0,0,14)
193 #define AT91_GPIO_PA15 AT91_PIN(0,0,15)
194 #define AT91_GPIO_PA16 AT91_PIN(0,0,16)
195 #define AT91_GPIO_PA17 AT91_PIN(0,0,17)
196 #define AT91_GPIO_PA18 AT91_PIN(0,0,18)
197 #define AT91_GPIO_PA19 AT91_PIN(0,0,19)
198 #define AT91_GPIO_PA20 AT91_PIN(0,0,20)
199 #define AT91_GPIO_PA21 AT91_PIN(0,0,21)
200 #define AT91_GPIO_PA22 AT91_PIN(0,0,22)
201 #define AT91_GPIO_PA23 AT91_PIN(0,0,23)
202 #define AT91_GPIO_PA24 AT91_PIN(0,0,24)
203 #define AT91_GPIO_PA25 AT91_PIN(0,0,25)
204 #define AT91_GPIO_PA26 AT91_PIN(0,0,26)
205 #define AT91_GPIO_PA27 AT91_PIN(0,0,27)
206 #define AT91_GPIO_PA28 AT91_PIN(0,0,28)
207 #define AT91_GPIO_PA29 AT91_PIN(0,0,29)
208 #define AT91_GPIO_PA30 AT91_PIN(0,0,30)
209 #define AT91_GPIO_PA31 AT91_PIN(0,0,31)
212 // GPIO pins on PIOB.
213 #define AT91_GPIO_PB0 AT91_PIN(1,0, 0)
214 #define AT91_GPIO_PB1 AT91_PIN(1,0, 1)
215 #define AT91_GPIO_PB2 AT91_PIN(1,0, 2)
216 #define AT91_GPIO_PB3 AT91_PIN(1,0, 3)
217 #define AT91_GPIO_PB4 AT91_PIN(1,0, 4)
218 #define AT91_GPIO_PB5 AT91_PIN(1,0, 5)
219 #define AT91_GPIO_PB6 AT91_PIN(1,0, 6)
220 #define AT91_GPIO_PB7 AT91_PIN(1,0, 7)
221 #define AT91_GPIO_PB8 AT91_PIN(1,0, 8)
222 #define AT91_GPIO_PB9 AT91_PIN(1,0, 9)
223 #define AT91_GPIO_PB10 AT91_PIN(1,0,10)
224 #define AT91_GPIO_PB11 AT91_PIN(1,0,11)
225 #define AT91_GPIO_PB12 AT91_PIN(1,0,12)
226 #define AT91_GPIO_PB13 AT91_PIN(1,0,13)
227 #define AT91_GPIO_PB14 AT91_PIN(1,0,14)
228 #define AT91_GPIO_PB15 AT91_PIN(1,0,15)
229 #define AT91_GPIO_PB16 AT91_PIN(1,0,16)
230 #define AT91_GPIO_PB17 AT91_PIN(1,0,17)
231 #define AT91_GPIO_PB18 AT91_PIN(1,0,18)
232 #define AT91_GPIO_PB19 AT91_PIN(1,0,19)
233 #define AT91_GPIO_PB20 AT91_PIN(1,0,20)
234 #define AT91_GPIO_PB21 AT91_PIN(1,0,21)
235 #define AT91_GPIO_PB22 AT91_PIN(1,0,22)
236 #define AT91_GPIO_PB23 AT91_PIN(1,0,23)
237 #define AT91_GPIO_PB24 AT91_PIN(1,0,24)
238 #define AT91_GPIO_PB25 AT91_PIN(1,0,25)
239 #define AT91_GPIO_PB26 AT91_PIN(1,0,26)
240 #define AT91_GPIO_PB27 AT91_PIN(1,0,27)
241 #define AT91_GPIO_PB28 AT91_PIN(1,0,28)
242 #define AT91_GPIO_PB29 AT91_PIN(1,0,29)
243 #define AT91_GPIO_PB30 AT91_PIN(1,0,30)
244 #define AT91_GPIO_PB31 AT91_PIN(1,0,31)
247 #if defined(CYGHWR_HAL_ARM_AT91_M55800A)
249 #define AT91_TC_TCLK3 AT91_PIN(0,0, 0) // Timer 3 Clock signal
250 #define AT91_TC_TIOA3 AT91_PIN(0,0, 1) // Timer 3 Signal A
251 #define AT91_TC_TIOB3 AT91_PIN(0,0, 2) // Timer 3 Signal B
252 #define AT91_TC_TCLK4 AT91_PIN(0,0, 3) // Timer 4 Clock signal
253 #define AT91_TC_TIOA4 AT91_PIN(0,0, 4) // Timer 4 Signal A
254 #define AT91_TC_TIOB4 AT91_PIN(0,0, 5) // Timer 4 Signal B
255 #define AT91_TC_TCLK5 AT91_PIN(0,0, 6) // Timer 5 Clock signal
256 #define AT91_TC_TIOA5 AT91_PIN(0,0, 7) // Timer 5 Signal A
257 #define AT91_TC_TIOB5 AT91_PIN(0,0, 8) // Timer 5 Signal B
258 #define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // External Interrupt 0
259 #define AT91_INT_IRQ1 AT91_PIN(0,0,10) // External Interrupt 1
260 #define AT91_INT_IRQ2 AT91_PIN(0,0,11) // External Interrupt 2
261 #define AT91_INT_IRQ3 AT91_PIN(0,0,12) // External Interrupt 3
262 #define AT91_INT_FIQ AT91_PIN(0,0,13) // Fast Interrupt
263 #define AT91_USART_SCK0 AT91_PIN(0,0,14) // USART 0 Clock signal
264 #define AT91_USART_TXD0 AT91_PIN(0,0,15) // USART 0 transmit data
265 #define AT91_USART_RXD0 AT91_PIN(0,0,16) // USART 0 receive data
266 #define AT91_USART_SCK1 AT91_PIN(0,0,17) // USART 1 Clock signal
267 #define AT91_USART_TXD1 AT91_PIN(0,0,18) // USART 1 transmit data
268 #define AT91_USART_RXD1 AT91_PIN(0,0,19) // USART 1 receive data
269 #define AT91_USART_SCK2 AT91_PIN(0,0,20) // USART 2 Clock signal
270 #define AT91_USART_TXD2 AT91_PIN(0,0,21) // USART 2 transmit data
271 #define AT91_USART_RXD2 AT91_PIN(0,0,22) // USART 2 receive data
272 #define AT91_SPI_SPCK AT91_PIN(0,0,23) // SPI Clock signal
273 #define AT91_SPI_MISO AT91_PIN(0,0,24) // SPI Master In Slave Out
274 #define AT91_SPI_MOIS AT91_PIN(0,0,25) // SPI Master Out Slave In
275 #define AT91_SPI_NPCS0 AT91_PIN(0,0,26) // SPI Peripheral Chip Select 0
276 #define AT91_SPI_NPCS1 AT91_PIN(0,0,27) // SPI Peripheral Chip Select 1
277 #define AT91_SPI_NPCS2 AT91_PIN(0,0,28) // SPI Peripheral Chip Select 2
278 #define AT91_SPI_NPCS3 AT91_PIN(0,0,29) // SPI Peripheral Chip Select 3
280 #define AT91_INT_IRQ4 AT91_PIN(1,0, 3) // External Interrupt 4
281 #define AT91_INT_IRQ5 AT91_PIN(1,0, 4) // External Interrupt 5
282 #define AT91_ADC_AD0TRIG AT91_PIN(1,0, 6) // ADC0 External Trigger
283 #define AT91_ADC_AD1TRIG AT91_PIN(1,0, 7) // ADC1 External Trigger
284 #define AT91_BOOT_BMS AT91_PIN(1,0,12) // Boot Mode Select
285 #define AT91_TC_TCLK0 AT91_PIN(1,0,14) // Timer 0 Clock signal
286 #define AT91_TC_TIOA0 AT91_PIN(1,0,15) // Timer 0 Signal A
287 #define AT91_TC_TIOB0 AT91_PIN(1,0,16) // Timer 0 Signal B
288 #define AT91_TC_TCLK1 AT91_PIN(1,0,17) // Timer 1 Clock signal
289 #define AT91_TC_TIOA1 AT91_PIN(1,0,18) // Timer 1 Signal A
290 #define AT91_TC_TIOB1 AT91_PIN(1,0,19) // Timer 1 Signal B
291 #define AT91_TC_TCLK2 AT91_PIN(1,0,20) // Timer 2 Clock signal
292 #define AT91_TC_TIOA2 AT91_PIN(1,0,21) // Timer 2 Signal A
293 #define AT91_TC_TIOB2 AT91_PIN(1,0,22) // Timer 2 Signal B
296 #define AT91_PIO_PSR_TCLK3 0x00000001 // Timer 3 Clock signal
297 #define AT91_PIO_PSR_TIOA3 0x00000002 // Timer 3 Signal A
298 #define AT91_PIO_PSR_TIOB3 0x00000004 // Timer 3 Signal B
299 #define AT91_PIO_PSR_TCLK4 0x00000008 // Timer 4 Clock signal
300 #define AT91_PIO_PSR_TIOA4 0x00000010 // Timer 4 Signal A
301 #define AT91_PIO_PSR_TIOB4 0x00000020 // Timer 4 Signal B
302 #define AT91_PIO_PSR_TCLK5 0x00000040 // Timer 5 Clock signal
303 #define AT91_PIO_PSR_TIOA5 0x00000080 // Timer 5 Signal A
304 #define AT91_PIO_PSR_TIOB5 0x00000100 // Timer 5 Signal B
305 #define AT91_PIO_PSR_IRQ0 0x00000200 // External Interrupt 0
306 #define AT91_PIO_PSR_IRQ1 0x00000400 // External Interrupt 1
307 #define AT91_PIO_PSR_IRQ2 0x00000800 // External Interrupt 2
308 #define AT91_PIO_PSR_IRQ3 0x00001000 // External Interrupt 3
309 #define AT91_PIO_PSR_FIQ 0x00002000 // Fast Interrupt
310 #define AT91_PIO_PSR_SCK0 0x00004000 // USART 0 Clock signal
311 #define AT91_PIO_PSR_TXD0 0x00008000 // USART 0 transmit data
312 #define AT91_PIO_PSR_RXD0 0x00010000 // USART 0 receive data
313 #define AT91_PIO_PSR_SCK1 0x00020000 // USART 1 Clock signal
314 #define AT91_PIO_PSR_TXD1 0x00040000 // USART 1 transmit data
315 #define AT91_PIO_PSR_RXD1 0x00080000 // USART 1 receive data
316 #define AT91_PIO_PSR_SCK2 0x00100000 // USART 2 Clock signal
317 #define AT91_PIO_PSR_TXD2 0x00200000 // USART 2 transmit data
318 #define AT91_PIO_PSR_RXD2 0x00400000 // USART 2 receive data
319 #define AT91_PIO_PSR_SPCK 0x00800000 // SPI Clock signal
320 #define AT91_PIO_PSR_MISO 0x01000000 // SPI Master In Slave Out
321 #define AT91_PIO_PSR_MOIS 0x02000000 // SPI Master Out Slave In
322 #define AT91_PIO_PSR_NPCS0 0x04000000 // SPI Peripheral Chip Select 0
323 #define AT91_PIO_PSR_NPCS1 0x08000000 // SPI Peripheral Chip Select 1
324 #define AT91_PIO_PSR_NPCS2 0x10000000 // SPI Peripheral Chip Select 2
325 #define AT91_PIO_PSR_NPCS3 0x20000000 // SPI Peripheral Chip Select 3
328 #define AT91_PIO_PSR_IRQ4 0x00000008 // External Interrupt 4
329 #define AT91_PIO_PSR_IRQ5 0x00000010 // External Interrupt 5
330 #define AT91_PIO_PSR_AD0TRIG 0x00000040 // ADC0 External Trigger
331 #define AT91_PIO_PSR_AD1TRIG 0x00000080 // ADC1 External Trigger
332 #define AT91_PIO_PSR_BMS 0x00040000 // Boot Mode Select
333 #define AT91_PIO_PSR_TCLK0 0x00080000 // Timer 0 Clock signal
334 #define AT91_PIO_PSR_TIOA0 0x00100000 // Timer 0 Signal A
335 #define AT91_PIO_PSR_TIOB0 0x00200000 // Timer 0 Signal B
336 #define AT91_PIO_PSR_TCLK1 0x00400000 // Timer 1 Clock signal
337 #define AT91_PIO_PSR_TIOA1 0x00800000 // Timer 1 Signal A
338 #define AT91_PIO_PSR_TIOB1 0x01000000 // Timer 1 Signal B
339 #define AT91_PIO_PSR_TCLK2 0x02000000 // Timer 2 Clock signal
340 #define AT91_PIO_PSR_TIOA2 0x04000000 // Timer 2 Signal A
341 #define AT91_PIO_PSR_TIOB2 0x08000000 // Timer 2 Signal B
343 #elif defined (CYGHWR_HAL_ARM_AT91SAM7)
344 #include <pkgconf/hal_arm_at91sam7.h>
346 #ifdef CYGHWR_HAL_ARM_AT91SAM7S
347 #define AT91_PWM_PWM0 AT91_PIN(0,0, 0) // Pulse Width Modulation 0
348 #define AT91_PWM_PWM1 AT91_PIN(0,0, 1) // Pulse Width Modulation 1
349 #define AT91_PWM_PWM2 AT91_PIN(0,0, 2) // Pulse Width Modulation 2
350 #define AT91_TWI_TWD AT91_PIN(0,0, 3) // Two Wire Data
351 #define AT91_TWI_TWCK AT91_PIN(0,0, 4) // Two Wire Clock
352 #define AT91_USART_RXD0 AT91_PIN(0,0, 5) // USART 0 Receive Data
353 #define AT91_USART_TXD0 AT91_PIN(0,0, 6) // USART 0 Transmit Data
354 #define AT91_USART_RTS0 AT91_PIN(0,0, 7) // USART 0 Ready To Send
355 #define AT91_USART_CTS0 AT91_PIN(0,0, 8) // USART 0 Clear To Send
356 #define AT91_DBG_DRXD AT91_PIN(0,0, 9) // Debug UART Receive
357 #define AT91_DBG_DTXD AT91_PIN(0,0,10) // Debug UART Transmit
358 #define AT91_SPI_NPCS0 AT91_PIN(0,0,11) // SPI Chip Select 0
359 #define AT91_SPI_MISO AT91_PIN(0,0,12) // SPI Input
360 #define AT91_SPI_MOIS AT91_PIN(0,0,13) // SPI Output
361 #define AT91_SPI_SPCK AT91_PIN(0,0,14) // SPI clock
362 #define AT91_S2C_TF AT91_PIN(0,0,15) // S2C Transmit Frame Sync
363 #define AT91_S2C_TK AT91_PIN(0,0,16) // S2C Transmit Clock
364 #define AT91_S2C_TD AT91_PIN(0,0,17) // S2C Transmit Data
365 #define AT91_S2C_RD AT91_PIN(0,0,18) // S2C Receive Data
366 #define AT91_S2C_RK AT91_PIN(0,0,19) // S2C Receive Clock
367 #define AT91_S2C_RF AT91_PIN(0,0,20) // S2C Receive Frame Sync
368 #if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
369 #define AT91_USART_RXD1 AT91_PIN(0,0,21) // USART 1 Receive Data
370 #define AT91_USART_TXD1 AT91_PIN(0,0,22) // USART 1 Transmit Data
371 #define AT91_USART_SCK1 AT91_PIN(0,0,23) // USART 1 Serial Clock
372 #define AT91_USART_RTS1 AT91_PIN(0,0,24) // USART 1 Ready To Send
373 #define AT91_USART_CTS1 AT91_PIN(0,0,25) // USART 1 Clear To Send
374 #define AT91_USART_DVD1 AT91_PIN(0,0,26) // USART 1 Data Carrier Detect
375 #define AT91_USART_DTR1 AT91_PIN(0,0,27) // USART 1 Data Terminal Ready
376 #define AT91_USART_DSR1 AT91_PIN(0,0,28) // USART 1 Data Set Ready
377 #define AT91_USART_RI1 AT91_PIN(0,0,29) // USART 2 Ring Indicator
378 #define AT91_INT_IRQ1 AT91_PIN(0,0,30) // Interrupt Request 1
379 #define AT91_SPI_NPCS1 AT91_PIN(0,0,31) // SPI Chip Select 1
382 #define AT91_TC_TIOA0 AT91_PIN(0,1, 0) // Timer/Counter 0 IO Line A
383 #define AT91_TC_TIOB0 AT91_PIN(0,1, 1) // Timer/Counter 0 IO Line B
384 #define AT91_USART_SCK0 AT91_PIN(0,1, 2) // USART 0 Serial Clock
385 #define AT91_SPI_NPCS3 AT91_PIN(0,1, 3) // SPI Chip Select 3
386 #define AT91_TC_TCLK0 AT91_PIN(0,1, 4) // Timer/Counter 0 Clock Input
387 #define AT91_SPI_NPCS3X AT91_PIN(0,1, 5) // SPI Chip Select 3 (again)
388 #define AT91_PCK_PCK0 AT91_PIN(0,1, 6) // Programmable Clock Output 0
389 #define AT91_PWM_PWM3 AT91_PIN(0,1, 7) // Pulse Width Modulation #3
390 #define AT91_ADC_ADTRG AT91_PIN(0,1, 8) // ADC Trigger
391 #define AT91_SPI_NPCS1X AT91_PIN(0,1, 9) // SPI Chip Select 1
392 #define AT91_SPI_NPCS2 AT91_PIN(0,1,10) // SPI Chip Select 2
393 #define AT91_PWM_PWM0X AT91_PIN(0,1,11) // Pulse Width Modulation #0
394 #define AT91_PIO_PWM_PWM1X AT91_PIN(0,1,12) // Pulse Width Modulation #1
395 #define AT91_PIO_PWM_PWM2X AT91_PIN(0,1,13) // Pulse Width Modulation #2
396 #define AT91_PIO_PWM_PWM4X AT91_PIN(0,1,14) // Pulse Width Modulation #4
397 #define AT91_TC_TIOA1 AT91_PIN(0,1,15) // Timer/Counter 1 IO Line A
398 #define AT91_TC_TIOB1 AT91_PIN(0,1,16) // Timer/Counter 1 IO Line B
399 #define AT91_PCK_PCK1 AT91_PIN(0,1,17) // Programmable Clock Output 1
400 #define AT91_PCK_PCK2 AT91_PIN(0,1,18) // Programmable Clock Output 2
401 #define AT91_INT_FIQ AT91_PIN(0,1,19) // Fast Interrupt Request
402 #define AT91_INT_IRQ0 AT91_PIN(0,1,20) // Interrupt Request 0
403 #if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
404 #define AT91_PCK_PCK1X AT91_PIN(0,1,21) // Programmable Clock Output 1
405 #define AT91_SPI_NPCS3XX AT91_PIN(0,1,22) // SPI Chip Select 3 (yet again)
406 #define AT91_PWM_PWM0XX AT91_PIN(0,1,23) // Pulse Width Modulation #0
407 #define AT91_PWM_PWM1XX AT91_PIN(0,1,24) // Pulse Width Modulation #1
408 #define AT91_PWM_PWM2XX AT91_PIN(0,1,25) // Pulse Width Modulation 2
409 #define AT91_TC_TIOA2 AT91_PIN(0,1,26) // Timer/Counter 2 IO Line A
410 #define AT91_TC_TIOB2 AT91_PIN(0,1,27) // Timer/Counter 2 IO Line B
411 #define AT91_TC_TCLK1 AT91_PIN(0,1,28) // External Clock Input 1
412 #define AT91_TC_TCLK2 AT91_PIN(0,1,29) // External Clock Input 2
413 #define AT91_SPI_NPCS2X AT91_PIN(0,1,30) // SPI Chip Select 2 (again)
414 #define AT91_PCK_PCK2X AT91_PIN(0,1,31) // Programmable Clock Output 2
415 #endif //!defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
418 #define AT91_PIO_PSR_PWM0 0x00000001 // Pulse Width Modulation 0
419 #define AT91_PIO_PSR_PWM1 0x00000002 // Pulse Width Modulation 1
420 #define AT91_PIO_PSR_PWM2 0x00000004 // Pulse Width Modulation 2
421 #define AT91_PIO_PSR_TWD 0x00000008 // Two Wire Data
422 #define AT91_PIO_PSR_TWCK 0x00000010 // Two Wire Clock
423 #define AT91_PIO_PSR_RXD0 0x00000020 // USART 0 Receive Data
424 #define AT91_PIO_PSR_TXD0 0x00000040 // USART 0 Transmit Data
425 #define AT91_PIO_PSR_RTS0 0x00000080 // USART 0 Ready To Send
426 #define AT91_PIO_PSR_CTS0 0x00000100 // USART 0 Clear To Send
427 #define AT91_PIO_PSR_DRXD 0x00000200 // Debug UART Receive
428 #define AT91_PIO_PSR_DTXD 0x00000400 // Debug UART Transmit
429 #define AT91_PIO_PSR_NPCS0 0x00000800 // SPI Chip Select 0
430 #define AT91_PIO_PSR_MISO 0x00001000 // SPI Input
431 #define AT91_PIO_PSR_MOIS 0x00002000 // SPI Output
432 #define AT91_PIO_PSR_SPCK 0x00004000 // SPI clock
433 #define AT91_PIO_PSR_TF 0x00008000 // S2C Transmit Frame Sync
434 #define AT91_PIO_PSR_TK 0x00010000 // S2C Transmit Clock
435 #define AT91_PIO_PSR_TD 0x00020000 // S2C Transmit Data
436 #define AT91_PIO_PSR_RD 0x00040000 // S2C Receive Data
437 #define AT91_PIO_PSR_RK 0x00080000 // S2C Receive Clock
438 #define AT91_PIO_PSR_RF 0x00100000 // S2C Receive Frame Sync
439 #if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
440 #define AT91_PIO_PSR_RXD1 0x00200000 // USART 1 Receive Data
441 #define AT91_PIO_PSR_TXD1 0x00400000 // USART 1 Transmit Data
442 #define AT91_PIO_PSR_SCK1 0x00800000 // USART 1 Serial Clock
443 #define AT91_PIO_PSR_RTS1 0x01000000 // USART 1 Ready To Send
444 #define AT91_PIO_PSR_CTS1 0x02000000 // USART 1 Clear To Send
445 #define AT91_PIO_PSR_DCD1 0x04000000 // USART 1 Data Carrier Detect
446 #define AT91_PIO_PSR_DTR1 0x08000000 // USART 1 Data Terminal Ready
447 #define AT91_PIO_PSR_DSR1 0x10000000 // USART 1 Data Set Ready
448 #define AT91_PIO_PSR_RI1 0x20000000 // USART 2 Ring Indicator
449 #define AT91_PIO_PSR_IRQ1 0x40000000 // Interrupt Request 1
450 #define AT91_PIO_PSR_NPCS1 0x80000000 // SPI Chip Select 1
451 #endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s64)
454 #define AT91_PIO_PSR_TIOA0 0x00000001 // Timer/Counter 0 IO Line A
455 #define AT91_PIO_PSR_TIOB0 0x00000002 // Timer/Counter 0 IO Line B
456 #define AT91_PIO_PSR_SCK0 0x00000004 // USART 0 Serial Clock
457 #define AT91_PIO_PSR_NPCS3 0x00000008 // SPI Chip Select 3
458 #define AT91_PIO_PSR_TCLK0 0x00000010 // Timer/Counter 0 Clock Input
459 #define AT91_PIO_PSR_NPCS3X 0x00000020 // SPI Chip Select 3 (again)
460 #define AT91_PIO_PSR_PCK0 0x00000040 // Programmable Clock Output 0
461 #define AT91_PIO_PSR_PWM3 0x00000080 // Pulse Width Modulation #3
462 #define AT91_PIO_PSR_ADTRG 0x00000100 // ADC Trigger
463 #define AT91_PIO_PSR_NPCS1X 0x00000200 // SPI Chip Select 1 (again)
464 #define AT91_PIO_PSR_NPCS2 0x00000400 // SPI Chip Select 2
465 #define AT91_PIO_PSR_PWMOX 0x00000800 // Pulse Width Modulation #0 (again)
466 #define AT91_PIO_PSR_PWM1X 0x00001000 // Pulse Width Modulation #1 (again)
467 #define AT91_PIO_PSR_PWM2X 0x00002000 // Pulse Width Modulation #2 (again)
468 #define AT91_PIO_PSR_PWM3X 0x00004000 // Pulse Width Modulation #4 (again)
469 #define AT91_PIO_PSR_TIOA1 0x00008000 // Timer/Counter 1 IO Line A
470 #define AT91_PIO_PSR_TIOB1 0x00010000 // Timer/Counter 1 IO Line B
471 #define AT91_PIO_PSR_PCK1 0x00020000 // Programmable Clock Output 1
472 #define AT91_PIO_PSR_PCK2 0x00040000 // Programmable Clock Output 2
473 #define AT91_PIO_PSR_FIQ 0x00080000 // Fast Interrupt Request
474 #define AT91_PIO_PSR_IRQ0 0x00100000 // Interrupt Request 0
475 #if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
476 #define AT91_PIO_PSR_PCK1X 0x00200000 // Programmable Clock Output 1(again)
477 #define AT91_PIO_PSR_NPCS3XX 0x00400000 // SPI Chip Select 3 (yet again)
478 #define AT91_PIO_PSR_PWMOXX 0x00800000 // Pulse Width Modulation #0 (again)
479 #define AT91_PIO_PSR_PWM1XX 0x01000000 // Pulse Width Modulation #1 (again)
480 #define AT91_PIO_PSR_PWM2XX 0x02000000 // Pulse Width Modulation #2 (again)
481 #define AT91_PIO_PSR_TIOA2 0x04000000 // Timer/Counter 2 IO Line A
482 #define AT91_PIO_PSR_TIOB2 0x08000000 // Timer/Counter 2 IO Line B
483 #define AT91_PIO_PSR_TCLK1 0x10000000 // External Clock Input 1
484 #define AT91_PIO_PSR_TCLK2 0x20000000 // External Clock Input 2
485 #define AT91_PIO_PSR_NPCS2X 0x40000000 // SPI Chip Select 2 (again)
486 #define AT91_PIO_PSR_PCK2X 0x80000000 // Programmable Clock Output 2(again)
487 #endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s64)
488 #endif // CYGHWR_HAL_ARM_AT91SAM7S
490 #ifdef CYGHWR_HAL_ARM_AT91SAM7X
492 // PIO Controller A, peripheral A
493 #define AT91_USART_RXD0 AT91_PIN(0,0, 0) // USART 0 Receive Data
494 #define AT91_USART_TXD0 AT91_PIN(0,0, 1) // USART 0 Transmit Data
495 #define AT91_USART_SCK0 AT91_PIN(0,0, 2) // USART 0 Serial Clock
496 #define AT91_USART_RTS0 AT91_PIN(0,0, 3) // USART 0 Request To Send
497 #define AT91_USART_CTS0 AT91_PIN(0,0, 4) // USART 0 Clear To Send
498 #define AT91_USART_RXD1 AT91_PIN(0,0, 5) // USART 1 Receive Data
499 #define AT91_USART_TXD1 AT91_PIN(0,0, 6) // USART 1 Transmit Data
500 #define AT91_USART_SCK1 AT91_PIN(0,0, 7) // USART 1 Serial Clock
501 #define AT91_USART_RTS1 AT91_PIN(0,0, 8) // USART 1 Request To Send
502 #define AT91_USART_CTS1 AT91_PIN(0,0, 9) // USART 1 Clear To Send
503 #define AT91_TWI_TWD AT91_PIN(0,0,10) // Two Wire Data
504 #define AT91_TWI_TWCK AT91_PIN(0,0,11) // Two Wire Clock
505 #define AT91_SPI_NPCS0 AT91_PIN(0,0,12) // SPI 0 Chip Select 0
506 #define AT91_SPI_NPCS1 AT91_PIN(0,0,13) // SPI 0 Chip Select 1
507 #define AT91_SPI_NPCS2 AT91_PIN(0,0,14) // SPI 0 Chip Select 2
508 #define AT91_SPI_NPCS3 AT91_PIN(0,0,15) // SPI 0 Chip Select 3
509 #define AT91_SPI_MISO AT91_PIN(0,0,16) // SPI 0 Master In Slave Out
510 #define AT91_SPI_MOIS AT91_PIN(0,0,17) // SPI 0 Master Out Slave In
511 #define AT91_SPI_SPCK AT91_PIN(0,0,18) // SPI 0 Clock
512 #define AT91_CAN_CANRX AT91_PIN(0,0,19) // CAN Receive
513 #define AT91_CAN_CANTX AT91_PIN(0,0,20) // CAN Transmit
514 #define AT91_SSC_TF AT91_PIN(0,0,21) // SSC Transmit Frame Sync
515 #define AT91_S2C_TK AT91_PIN(0,0,22) // SSC Transmit Clock
516 #define AT91_S2C_TD AT91_PIN(0,0,23) // SSC Transmit Data
517 #define AT91_S2C_RD AT91_PIN(0,0,24) // SSC Receive Data
518 #define AT91_S2C_RK AT91_PIN(0,0,25) // SSC Receive Clock
519 #define AT91_S2C_RF AT91_PIN(0,0,26) // SSC Receive Frame Sync
520 #define AT91_DBG_DRXD AT91_PIN(0,0,27) // DBGU Receive Data
521 #define AT91_DBG_DTXD AT91_PIN(0,0,28) // DBGU Transmit Data
522 #define AT91_INT_FIQ AT91_PIN(0,0,29) // Fast Interrupt Request
523 #define AT91_INT_IRQ0 AT91_PIN(0,0,30) // Interrupt Request 0
525 //PIO controller A, peripheral B
526 #define AT91_SPI1_NPCS1 AT91_PIN(0,1, 2) // SPI 1 Chip Select 1
527 #define AT91_SPI1_NPCS2 AT91_PIN(0,1, 3) // SPI 1 Chip Select 2
528 #define AT91_SPI1_NPCS3 AT91_PIN(0,1, 4) // SPI 1 Chip Select 3
529 #define AT91_SPI_NPCS1X AT91_PIN(0,1, 7) // SPI 0 Chip Select 1
530 #define AT91_SPI_NPCS2X AT91_PIN(0,1, 8) // SPI 0 Chip Select 2
531 #define AT91_SPI_NPCS3X AT91_PIN(0,1, 9) // SPI 0 Chip Select 3
532 #define AT91_PCK_PCK1 AT91_PIN(0,1,13) // Programmable Clock Output 1
533 #define AT91_INT_IRQ1 AT91_PIN(0,1,14) // Interrupt Request 1
534 #define AT91_TC_TCLK1 AT91_PIN(0,1,15) // Timer/Counter 1 Clock Input
535 #define AT91_SPI1_NPCS0 AT91_PIN(0,1,21) // SPI 1 Chip Select 0
536 #define AT91_SPI1_SPCK AT91_PIN(0,1,22) // SPI 1 Clock
537 #define AT91_SPI1_MOSI AT91_PIN(0,1,23) // SPI 1 Master Out Slave In
538 #define AT91_SPI1_MISO AT91_PIN(0,1,24) // SPI 0 Master In Slave Out
539 #define AT91_SPI1_NPCS1X AT91_PIN(0,1,25) // SPI 1 Chip Select 1
540 #define AT91_SPI1_NPCS2X AT91_PIN(0,1,26) // SPI 1 Chip Select 2
541 #define AT91_PCK_PCK3 AT91_PIN(0,1,27) // Programmable Clock Output 3
542 #define AT91_SPI1_NPCS3X AT91_PIN(0,1,29) // SPI 1 Chip Select 3
543 #define AT91_PCK_PCK2 AT91_PIN(0,1,30) // Programmable Clock Output 2
545 //PIO Controller B, Peripheral A
546 #define AT91_EMAC_EREFCK AT91_PIN(1,0, 0) // EMAC Reference Clock
547 #define AT91_EMAC_ETXEN AT91_PIN(1,0, 1) // EMAC Transmit Enable
548 #define AT91_EMAC_ETX0 AT91_PIN(1,0, 2) // EMAC Transmit Data 0
549 #define AT91_EMAC_ETX1 AT91_PIN(1,0, 3) // EMAC Transmit Data 1
550 #define AT91_EMAC_ECRS AT91_PIN(1,0, 4) // EMAC Carrier Sense
551 #define AT91_EMAC_ERX0 AT91_PIN(1,0, 5) // EMAC Receive Data 0
552 #define AT91_EMAC_ERX1 AT91_PIN(1,0, 6) // EMAC Receive Data 1
553 #define AT91_EMAC_ERXER AT91_PIN(1,0, 7) // EMAC Receive Error
554 #define AT91_EMAC_EMDC AT91_PIN(1,0, 8) // EMAC Management Data Clock
555 #define AT91_EMAC_EMDIO AT91_PIN(1,0, 9) // EMAC Management Data IO
556 #define AT91_EMAC_ETX2 AT91_PIN(1,0,10) // EMAC Transmit Data 2
557 #define AT91_EMAC_ETX3 AT91_PIN(1,0,11) // EMAC Transmit Data 3
558 #define AT91_EMAC_ETXER AT91_PIN(1,0,12) // EMAC Transmit Coding Error
559 #define AT91_EMAC_ERX2 AT91_PIN(1,0,13) // EMAC Receive Data 2
560 #define AT91_EMAC_ERX3 AT91_PIN(1,0,14) // EMAC Receive Data 3
561 #define AT91_EMAC_ECRSDV AT91_PIN(1,0,15) // EMAC Carrier Sense And Data Valid
562 #define AT91_EMAC_ERXDV AT91_PIN(1,0,15) // EMAC Receive Data Valid
563 #define AT91_EMAC_ECOL AT91_PIN(1,0,16) // EMAC Collision Detected
564 #define AT91_EMAC_ERXCK AT91_PIN(1,0,17) // EMAC Receive Clock
565 #define AT91_EMAC_EF100 AT91_PIN(1,0,18) // EMAC Force 100Mb/s
566 #define AT91_PWM_PWM0 AT91_PIN(1,0,19) // Pulse Width Modulation #0
567 #define AT91_PWM_PWM1 AT91_PIN(1,0,20) // Pulse Width Modulation #1
568 #define AT91_PWM_PWM2 AT91_PIN(1,0,21) // Pulse Width Modulation #2
569 #define AT91_PWM_PWM3 AT91_PIN(1,0,22) // Pulse Width Modulation #3
570 #define AT91_TC_TIOA0 AT91_PIN(1,0,23) // Timer/Counter 0 IO Line A
571 #define AT91_TC_TIOB0 AT91_PIN(1,0,24) // Timer/Counter 0 IO Line B
572 #define AT91_TC_TIOA1 AT91_PIN(1,0,25) // Timer/Counter 1 IO Line A
573 #define AT91_TC_TIOB1 AT91_PIN(1,0,26) // Timer/Counter 1 IO Line B
574 #define AT91_TC_TIOA2 AT91_PIN(1,0,27) // Timer/Counter 2 IO Line A
575 #define AT91_TC_TIOB2 AT91_PIN(1,0,28) // Timer/Counter 2 IO Line B
576 #define AT91_PCK_PCK1X AT91_PIN(1,0,29) // Programmable Clock Output 1
577 #define AT91_PCK_PCK2X AT91_PIN(1,0,30) // Programmable Clock Output 2
579 //PIO Controller B Peripheral B
580 #define AT91_PCK_PCK0 AT91_PIN(1,1, 0) // Programmable Clock Output 0
581 #define AT91_SPI1_NPCS1XX AT91_PIN(1,1,10) // SPI 1 Chip Select 1
582 #define AT91_SPI1_NPCS2XX AT91_PIN(1,1,11) // SPI 1 Chip Select 2
583 #define AT91_TC_TCLK0 AT91_PIN(1,1,12) // Timer/Counter 0 Clock Input
584 #define AT91_SPI_NPCS1XX AT91_PIN(1,1,13) // SPI 0 Chip Select 1
585 #define AT91_SPI_NPCS2XX AT91_PIN(1,1,14) // SPI 0 Chip Select 2
586 #define AT91_SPI1_NPCS3XX AT91_PIN(1,1,16) // SPI 1 Chip Select 3
587 #define AT91_SPI_NPCS3XX AT91_PIN(1,1,17) // SPI 0 Chip Select 3
588 #define AT91_ADC_ADTRG AT91_PIN(1,1,18) // ADC Trigger
589 #define AT91_TC_TCLK1X AT91_PIN(1,1,19) // Timer/Counter 1 Clock Input
590 #define AT91_PCK_PCK0X AT91_PIN(1,1,20) // Programmable Clock Output 0
591 #define AT91_PCK_PCK1XX AT91_PIN(1,1,21) // Programmable Clock Output 1
592 #define AT91_PCK_PCK2XX AT91_PIN(1,1,22) // Programmable Clock Output 2
593 #define AT91_USART_DCD1 AT91_PIN(1,1,23) // USART 1 Data Carrier Detect
594 #define AT91_USART_DSR1 AT91_PIN(1,1,24) // USART 1 Data Set Ready
595 #define AT91_USART_DTR1 AT91_PIN(1,1,25) // USART 1 Data Terminal Ready
596 #define AT91_USART_RI1 AT91_PIN(1,1,26) // USART 1 Ring Indication
597 #define AT91_PWM_PWM0X AT91_PIN(1,1,27) // Pulse Width Modulation #0
598 #define AT91_PWM_PWM1X AT91_PIN(1,1,28) // Pulse Width Modulation #1
599 #define AT91_PWM_PWM2X AT91_PIN(1,1,29) // Pulse Width Modulation #2
600 #define AT91_PWM_PWM3X AT91_PIN(1,1,30) // Pulse Width Modulation #3
602 // PIO Controller A, peripheral A
603 #define AT91_PIO_PSR_RXD0 (1<< 0) // USART 0 Receive Data
604 #define AT91_PIO_PSR_TXD0 (1<< 1) // USART 0 Transmit Data
605 #define AT91_PIO_PSR_SCK0 (1<< 2) // USART 0 Serial Clock
606 #define AT91_PIO_PSR_RTS0 (1<< 3) // USART 0 Request To Send
607 #define AT91_PIO_PSR_CTS0 (1<< 4) // USART 0 Clear To Send
608 #define AT91_PIO_PSR_RXD1 (1<< 5) // USART 1 Receive Data
609 #define AT91_PIO_PSR_TXD1 (1<< 6) // USART 1 Transmit Data
610 #define AT91_PIO_PSR_SCK1 (1<< 7) // USART 1 Serial Clock
611 #define AT91_PIO_PSR_RTS1 (1<< 8) // USART 1 Request To Send
612 #define AT91_PIO_PSR_CTS1 (1<< 9) // USART 1 Clear To Send
613 #define AT91_PIO_PSR_TWD (1<<10) // Two Wire Data
614 #define AT91_PIO_PSR_TWCK (1<<11) // Two Wire Clock
615 #define AT91_PIO_PSR_SPI_NPCS0 (1<<12) // SPI 0 Chip Select 0
616 #define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1
617 #define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2
618 #define AT91_PIO_PSR_SPI_NPCS3 (1<<15) // SPI 0 Chip Select 3
619 #define AT91_PIO_PSR_SPI_MISO (1<<16) // SPI 0 Master In Slave Out
620 #define AT91_PIO_PSR_SPI_MOSI (1<<17) // SPI 0 Master Out Slave In
621 #define AT91_PIO_PSR_SPI_SPCK (1<<18) // SPI 0 Clock
622 #define AT91_PIO_PSR_CANRX (1<<19) // CAN Receive
623 #define AT91_PIO_PSR_CANTX (1<<20) // CAN Transmit
624 #define AT91_PIO_PSR_TF (1<<21) // SSC Transmit Frame Sync
625 #define AT91_PIO_PSR_TK (1<<22) // SSC Transmit Clock
626 #define AT91_PIO_PSR_TD (1<<23) // SSC Transmit Data
627 #define AT91_PIO_PSR_RD (1<<24) // SSC Receive Data
628 #define AT91_PIO_PSR_RK (1<<25) // SSC Receive Clock
629 #define AT91_PIO_PSR_RF (1<<26) // SSC Receive Frame Sync
630 #define AT91_PIO_PSR_DRXD (1<<27) // DBGU Receive Data
631 #define AT91_PIO_PSR_DTXD (1<<28) // DBGU Transmit Data
632 #define AT91_PIO_PSR_FIQ (1<<29) // Fast Interrupt Request
633 #define AT91_PIO_PSR_IRQ0 (1<<30) // Interrupt Request 0
635 //PIO controller A, peripheral B
636 #define AT91_PIO_PSR_SPI1_NPCS1 (1<< 2) // SPI 1 Chip Select 1
637 #define AT91_PIO_PSR_SPI1_NPCS2 (1<< 3) // SPI 1 Chip Select 2
638 #define AT91_PIO_PSR_SPI1_NPCS3 (1<< 4) // SPI 1 Chip Select 3
639 #define AT91_PIO_PSR_SPI_NPCS1X (1<< 7) // SPI 0 Chip Select 1
640 #define AT91_PIO_PSR_SPI_NPCS2X (1<< 8) // SPI 0 Chip Select 2
641 #define AT91_PIO_PSR_SPI_NPCS3X (1<< 9) // SPI 0 Chip Select 3
642 #define AT91_PIO_PSR_PCK1 (1<<13) // Programmable Clock Output 1
643 #define AT91_PIO_PSR_IRQ1 (1<<14) // Interrupt Request 1
644 #define AT91_PIO_PSR_TCLK1 (1<<15) // Timer/Counter 1 Clock Input
645 #define AT91_PIO_PSR_SPI1_NPCS0 (1<<21) // SPI 1 Chip Select 0
646 #define AT91_PIO_PSR_SPI1_SPCK (1<<22) // SPI 1 Clock
647 #define AT91_PIO_PSR_SPI1_MOSI (1<<23) // SPI 1 Master Out Slave In
648 #define AT91_PIO_PSR_SPI1_MISO (1<<24) // SPI 0 Master In Slave Out
649 #define AT91_PIO_PSR_SPI1_NPCS1X (1<<25) // SPI 1 Chip Select 1
650 #define AT91_PIO_PSR_SPI1_NPCS2X (1<<26) // SPI 1 Chip Select 2
651 #define AT91_PIO_PSR_PCK3 (1<<27) // Programmable Clock Output 3
652 #define AT91_PIO_PSR_SPI1_NPCS3X (1<<29) // SPI 1 Chip Select 3
653 #define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2
655 //PIO Controller B, Peripheral A
656 #define AT91_PIO_PSR_EREFCK (1<< 0) // EMAC Reference Clock
657 #define AT91_PIO_PSR_ETXEN (1<< 1) // EMAC Transmit Enable
658 #define AT91_PIO_PSR_ETX0 (1<< 2) // EMAC Transmit Data 0
659 #define AT91_PIO_PSR_ETX1 (1<< 3) // EMAC Transmit Data 1
660 #define AT91_PIO_PSR_ECRS (1<< 4) // EMAC Carrier Sense
661 #define AT91_PIO_PSR_ERX0 (1<< 5) // EMAC Receive Data 0
662 #define AT91_PIO_PSR_ERX1 (1<< 6) // EMAC Receive Data 1
663 #define AT91_PIO_PSR_ERXER (1<< 7) // EMAC Receive Error
664 #define AT91_PIO_PSR_EMDC (1<< 8) // EMAC Management Data Clock
665 #define AT91_PIO_PSR_EMDIO (1<< 9) // EMAC Management Data IO
666 #define AT91_PIO_PSR_ETX2 (1<<10) // EMAC Transmit Data 2
667 #define AT91_PIO_PSR_ETX3 (1<<11) // EMAC Transmit Data 3
668 #define AT91_PIO_PSR_ETXER (1<<12) // EMAC Transmit Coding Error
669 #define AT91_PIO_PSR_ERX2 (1<<13) // EMAC Receive Data 2
670 #define AT91_PIO_PSR_ERX3 (1<<14) // EMAC Receive Data 3
671 #define AT91_PIO_PSR_ECRSDV (1<<15) // EMAC Carrier Sense And Data Valid
672 #define AT91_PIO_PSR_ECOL (1<<16) // EMAC Collision Detected
673 #define AT91_PIO_PSR_ERXCK (1<<17) // EMAC Receive Clock
674 #define AT91_PIO_PSR_EF100 (1<<18) // EMAC Force 100Mb/s
675 #define AT91_PIO_PSR_PWM0 (1<<19) // Pulse Width Modulation #0
676 #define AT91_PIO_PSR_PWM1 (1<<20) // Pulse Width Modulation #1
677 #define AT91_PIO_PSR_PWM2 (1<<21) // Pulse Width Modulation #2
678 #define AT91_PIO_PSR_PWM3 (1<<22) // Pulse Width Modulation #3
679 #define AT91_PIO_PSR_TIOA0 (1<<23) // Timer/Counter 0 IO Line A
680 #define AT91_PIO_PSR_TIOB0 (1<<24) // Timer/Counter 0 IO Line B
681 #define AT91_PIO_PSR_TIOA1 (1<<25) // Timer/Counter 1 IO Line A
682 #define AT91_PIO_PSR_TIOB1 (1<<26) // Timer/Counter 1 IO Line B
683 #define AT91_PIO_PSR_TIOA2 (1<<27) // Timer/Counter 2 IO Line A
684 #define AT91_PIO_PSR_TIOB2 (1<<28) // Timer/Counter 2 IO Line B
685 #define AT91_PIO_PSR_PCK1X (1<<29) // Programmable Clock Output 1
686 #define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2
688 //PIO Controller B Peripheral B
689 #define AT91_PIO_PSR_PCK0 (1<< 0) // Programmable Clock Output 0
690 #define AT91_PIO_PSR_SPI1_NPCS1XX (1<<10) // SPI 1 Chip Select 1
691 #define AT91_PIO_PSR_SPI1_NPCS2XX (1<<11) // SPI 1 Chip Select 2
692 #define AT91_PIO_PSR_TCLK0 (1<<12) // Timer/Counter 0 Clock Input
693 #define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1
694 #define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2
695 #define AT91_PIO_PSR_SPI1_NPCS3XX (1<<16) // SPI 1 Chip Select 3
696 #define AT91_PIO_PSR_SPI_NPCS3XX (1<<17) // SPI 0 Chip Select 3
697 #define AT91_PIO_PSR_ADTRG (1<<18) // ADC Trigger
698 #define AT91_PIO_PSR_TCLK1X (1<<19) // Timer/Counter 1 Clock Input
699 #define AT91_PIO_PSR_PCK0X (1<<20) // Programmable Clock Output 0
700 #define AT91_PIO_PSR_PCK1XX (1<<21) // Programmable Clock Output 1
701 #define AT91_PIO_PSR_PCK2X (1<<22) // Programmable Clock Output 2
702 #define AT91_PIO_PSR_DCD1 (1<<23) // USART 1 Data Carrier Detect
703 #define AT91_PIO_PSR_DSR1 (1<<24) // USART 1 Data Set Ready
704 #define AT91_PIO_PSR_DTR1 (1<<25) // USART 1 Data Terminal Ready
705 #define AT91_PIO_PSR_RI1 (1<<26) // USART 1 Ring Indication
706 #define AT91_PIO_PSR_PWM0X (1<<27) // Pulse Width Modulation #0
707 #define AT91_PIO_PSR_PWM1X (1<<28) // Pulse Width Modulation #1
708 #define AT91_PIO_PSR_PWM2X (1<<29) // Pulse Width Modulation #2
709 #define AT91_PIO_PSR_PWM3X (1<<30) // Pulse Width Modulation #3
712 #ifdef CYGHWR_HAL_ARM_AT91SAM7XC
713 #error Sorry, still missing. Happy typing
717 #define AT91_TC_TCLK0 AT91_PIN(0,0, 0) // Timer #0 clock
718 #define AT91_TC_TIOA0 AT91_PIN(0,0, 1) // Timer #0 signal A
719 #define AT91_TC_TIOB0 AT91_PIN(0,0, 2) // Timer #0 signal B
720 #define AT91_TC_TCLK1 AT91_PIN(0,0, 3) // Timer #1 clock
721 #define AT91_TC_TIOA1 AT91_PIN(0,0, 4) // Timer #1 signal A
722 #define AT91_TC_TIOB1 AT91_PIN(0,0, 5) // Timer #1 signal B
723 #define AT91_TC_TCLK2 AT91_PIN(0,0, 6) // Timer #2 clock
724 #define AT91_TC_TIOA2 AT91_PIN(0,0, 7) // Timer #2 signal A
725 #define AT91_TC_TIOB2 AT91_PIN(0,0, 8) // Timer #2 signal B
726 #define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // IRQ #0
727 #define AT91_INT_IRQ1 AT91_PIN(0,0,10) // IRQ #1
728 #define AT91_INT_IRQ2 AT91_PIN(0,0,11) // IRQ #2
729 #define AT91_INT_FIQ AT91_PIN(0,0,12) // FIQ
730 #define AT91_USART_SCK0 AT91_PIN(0,0,13) // Serial port #0 clock
731 #define AT91_USART_TXD0 AT91_PIN(0,0,14) // Serial port #0 TxD
732 #define AT91_USART_RXD0 AT91_PIN(0,0,15) // Serial port #0 RxD
733 #define AT91_USART_SCK1 AT91_PIN(0,0,20) // Serial port #1 clock
734 #define AT91_USART_TXD1 AT91_PIN(0,0,21) // Serial port #1 TxD
735 #define AT91_USART_RXD1 AT91_PIN(0,0,22) // Serial port #1 RxD
736 #define AT91_CLK_MCKO AT91_PIN(0,0,25) // Master clock out
738 #define AT91_PIO_PSR_TCLK0 0x00000001 // Timer #0 clock
739 #define AT91_PIO_PSR_TIOA0 0x00000002 // Timer #0 signal A
740 #define AT91_PIO_PSR_TIOB0 0x00000004 // Timer #0 signal B
741 #define AT91_PIO_PSR_TCLK1 0x00000008 // Timer #1 clock
742 #define AT91_PIO_PSR_TIOA1 0x00000010 // Timer #1 signal A
743 #define AT91_PIO_PSR_TIOB1 0x00000020 // Timer #1 signal B
744 #define AT91_PIO_PSR_TCLK2 0x00000040 // Timer #2 clock
745 #define AT91_PIO_PSR_TIOA2 0x00000080 // Timer #2 signal A
746 #define AT91_PIO_PSR_TIOB2 0x00000100 // Timer #2 signal B
747 #define AT91_PIO_PSR_IRQ0 0x00000200 // IRQ #0
748 #define AT91_PIO_PSR_IRQ1 0x00000400 // IRQ #1
749 #define AT91_PIO_PSR_IRQ2 0x00000800 // IRQ #2
750 #define AT91_PIO_PSR_FIQ 0x00001000 // FIQ
751 #define AT91_PIO_PSR_SCK0 0x00002000 // Serial port #0 clock
752 #define AT91_PIO_PSR_TXD0 0x00004000 // Serial port #0 TxD
753 #define AT91_PIO_PSR_RXD0 0x00008000 // Serial port #0 RxD
754 #define AT91_PIO_PSR_P16 0x00010000 // PIO port #16
755 #define AT91_PIO_PSR_P17 0x00020000 // PIO port #17
756 #define AT91_PIO_PSR_P18 0x00040000 // PIO port #18
757 #define AT91_PIO_PSR_P19 0x00080000 // PIO port #19
758 #define AT91_PIO_PSR_SCK1 0x00100000 // Serial port #1 clock
759 #define AT91_PIO_PSR_TXD1 0x00200000 // Serial port #1 TxD
760 #define AT91_PIO_PSR_RXD1 0x00400000 // Serial port #1 RxD
761 #define AT91_PIO_PSR_P23 0x00800000 // PIO port #23
762 #define AT91_PIO_PSR_P24 0x01000000 // PIO port #24
763 #define AT91_PIO_PSR_MCKO 0x02000000 // Master clock out
764 #define AT91_PIO_PSR_NCS2 0x04000000 // Chip select #2
765 #define AT91_PIO_PSR_NCS3 0x08000000 // Chip select #3
766 #define AT91_PIO_PSR_CS7_A20 0x10000000 // Chip select #7 or A20
767 #define AT91_PIO_PSR_CS6_A21 0x20000000 // Chip select #6 or A21
768 #define AT91_PIO_PSR_CS5_A22 0x40000000 // Chip select #5 or A22
769 #define AT91_PIO_PSR_CS4_A23 0x80000000 // Chip select #4 or A23
772 #define AT91_PIO_OER 0x10 // Output enable
773 #define AT91_PIO_ODR 0x14 // Output disable
774 #define AT91_PIO_OSR 0x18 // Output status
775 #define AT91_PIO_IFER 0x20 // Input Filter enable
776 #define AT91_PIO_IFDR 0x24 // Input Filter disable
777 #define AT91_PIO_IFSR 0x28 // Input Filter status
778 #define AT91_PIO_SODR 0x30 // Set out bits
779 #define AT91_PIO_CODR 0x34 // Clear out bits
780 #define AT91_PIO_ODSR 0x38 // Output data status
781 #define AT91_PIO_PDSR 0x3C // Pin data status
782 #define AT91_PIO_IER 0x40 // Interrupt enable
783 #define AT91_PIO_IDR 0x44 // Interrupt disable
784 #define AT91_PIO_IMR 0x48 // Interrupt mask
785 #define AT91_PIO_ISR 0x4C // Interrupt status
787 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
788 #define AT91_PIO_MDER 0x50 // Multi-drive Enable Register
789 #define AT91_PIO_MDDR 0x54 // Multi-drive Disable Register
790 #define AT91_PIO_MDSR 0x58 // Multi-drive Status Register
791 #define AT91_PIO_PPUDR 0x60 // Pad Pull-up Disable Register
792 #define AT91_PIO_PPUER 0x64 // Pad Pull-up Enable Register
793 #define AT91_PIO_PPUSR 0x68 // Pad Pull-Up Status Register
794 #define AT91_PIO_ASR 0x70 // Select A Register
795 #define AT91_PIO_BSR 0x74 // Select B Regsiter
796 #define AT91_PIO_ABS 0x78 // AB Select Regsiter
797 #define AT91_PIO_OWER 0xa0 // Output Write Enable Register
798 #define AT91_PIO_OWDR 0xa4 // Output Write Disable Register
799 #define AT91_PIO_OWSR 0xa8 // Output Write Status Register
800 #endif // CYGHWR_HAL_ARM_AT91SAM7
802 //=============================================================================
803 // Advanced Interrupt Controller (AIC)
806 #define AT91_AIC 0xFFFFF000
809 #define AT91_AIC_SMR0 ((0*4)+0x000)
810 #define AT91_AIC_SMR1 ((1*4)+0x000)
811 #define AT91_AIC_SMR2 ((2*4)+0x000)
812 #define AT91_AIC_SMR3 ((3*4)+0x000)
813 #define AT91_AIC_SMR4 ((4*4)+0x000)
814 #define AT91_AIC_SMR5 ((5*4)+0x000)
815 #define AT91_AIC_SMR6 ((6*4)+0x000)
816 #define AT91_AIC_SMR7 ((7*4)+0x000)
817 #define AT91_AIC_SMR8 ((8*4)+0x000)
818 #define AT91_AIC_SMR9 ((9*4)+0x000)
819 #define AT91_AIC_SMR10 ((10*4)+0x000)
820 #define AT91_AIC_SMR11 ((11*4)+0x000)
821 #define AT91_AIC_SMR12 ((12*4)+0x000)
822 #define AT91_AIC_SMR13 ((13*4)+0x000)
823 #define AT91_AIC_SMR14 ((14*4)+0x000)
824 #define AT91_AIC_SMR15 ((15*4)+0x000)
825 #define AT91_AIC_SMR16 ((16*4)+0x000)
826 #define AT91_AIC_SMR17 ((17*4)+0x000)
827 #define AT91_AIC_SMR18 ((18*4)+0x000)
828 #define AT91_AIC_SMR19 ((19*4)+0x000)
829 #define AT91_AIC_SMR20 ((20*4)+0x000)
830 #define AT91_AIC_SMR21 ((21*4)+0x000)
831 #define AT91_AIC_SMR22 ((22*4)+0x000)
832 #define AT91_AIC_SMR23 ((23*4)+0x000)
833 #define AT91_AIC_SMR24 ((24*4)+0x000)
834 #define AT91_AIC_SMR25 ((25*4)+0x000)
835 #define AT91_AIC_SMR26 ((26*4)+0x000)
836 #define AT91_AIC_SMR27 ((27*4)+0x000)
837 #define AT91_AIC_SMR28 ((28*4)+0x000)
838 #define AT91_AIC_SMR29 ((29*4)+0x000)
839 #define AT91_AIC_SMR30 ((30*4)+0x000)
840 #define AT91_AIC_SMR31 ((31*4)+0x000)
841 #define AT91_AIC_SMR_LEVEL_LOW (0<<5)
842 #define AT91_AIC_SMR_LEVEL_HI (2<<5)
843 #define AT91_AIC_SMR_EDGE_NEG (1<<5)
844 #define AT91_AIC_SMR_EDGE_POS (3<<5)
845 #define AT91_AIC_SMR_PRIORITY 0x07
846 #define AT91_AIC_SVR0 ((0*4)+0x080)
847 #define AT91_AIC_SVR1 ((1*4)+0x080)
848 #define AT91_AIC_SVR2 ((2*4)+0x080)
849 #define AT91_AIC_SVR3 ((3*4)+0x080)
850 #define AT91_AIC_SVR4 ((4*4)+0x080)
851 #define AT91_AIC_SVR5 ((5*4)+0x080)
852 #define AT91_AIC_SVR6 ((6*4)+0x080)
853 #define AT91_AIC_SVR7 ((7*4)+0x080)
854 #define AT91_AIC_SVR8 ((8*4)+0x080)
855 #define AT91_AIC_SVR9 ((9*4)+0x080)
856 #define AT91_AIC_SVR10 ((10*4)+0x080)
857 #define AT91_AIC_SVR11 ((11*4)+0x080)
858 #define AT91_AIC_SVR12 ((12*4)+0x080)
859 #define AT91_AIC_SVR13 ((13*4)+0x080)
860 #define AT91_AIC_SVR14 ((14*4)+0x080)
861 #define AT91_AIC_SVR15 ((15*4)+0x080)
862 #define AT91_AIC_SVR16 ((16*4)+0x080)
863 #define AT91_AIC_SVR17 ((17*4)+0x080)
864 #define AT91_AIC_SVR18 ((18*4)+0x080)
865 #define AT91_AIC_SVR19 ((19*4)+0x080)
866 #define AT91_AIC_SVR20 ((20*4)+0x080)
867 #define AT91_AIC_SVR21 ((21*4)+0x080)
868 #define AT91_AIC_SVR22 ((22*4)+0x080)
869 #define AT91_AIC_SVR23 ((23*4)+0x080)
870 #define AT91_AIC_SVR24 ((24*4)+0x080)
871 #define AT91_AIC_SVR25 ((25*4)+0x080)
872 #define AT91_AIC_SVR26 ((26*4)+0x080)
873 #define AT91_AIC_SVR27 ((27*4)+0x080)
874 #define AT91_AIC_SVR28 ((28*4)+0x080)
875 #define AT91_AIC_SVR29 ((29*4)+0x080)
876 #define AT91_AIC_SVR30 ((30*4)+0x080)
877 #define AT91_AIC_SVR31 ((31*4)+0x080)
878 #define AT91_AIC_IVR 0x100
879 #define AT91_AIC_FVR 0x104
880 #define AT91_AIC_ISR 0x108
881 #define AT91_AIC_IPR 0x10C
882 #define AT91_AIC_IMR 0x110
883 #define AT91_AIC_CISR 0x114
884 #define AT91_AIC_IECR 0x120
885 #define AT91_AIC_IDCR 0x124
886 #define AT91_AIC_ICCR 0x128
887 #define AT91_AIC_ISCR 0x12C
888 #define AT91_AIC_EOI 0x130
889 #define AT91_AIC_SVR 0x134
891 #ifdef CYGHWR_HAL_ARM_AT91SAM7
892 #define AT91_AIC_DCR 0x138 // Debug Control Register
893 #define AT91_AIC_FFER 0x140 // Fast Forcing Enable Register
894 #define AT91_AIC_FFDR 0x144 // Fast Forcing Enable Register
895 #define AT91_AIC_FFSR 0x148 // Fast Forcing Enable Register
896 #endif // CYGHWR_HAL_ARM_AT91SAM7
898 //=============================================================================
902 #define AT91_TC 0xFFFE0000
905 #define AT91_TC_TC0 0x00
906 #define AT91_TC_TC1 0x40
907 #define AT91_TC_TC2 0x80
908 #define AT91_TC_TC_SIZE 0x40
910 #define AT91_TC_CCR 0x00
911 #define AT91_TC_CCR_CLKEN 0x01
912 #define AT91_TC_CCR_CLKDIS 0x02
913 #define AT91_TC_CCR_TRIG 0x04
914 // Channel Mode Register
915 #define AT91_TC_CMR 0x04
916 #define AT91_TC_CMR_CLKS 0
917 #define AT91_TC_CMR_CLKS_MCK2 (0<<0)
918 #define AT91_TC_CMR_CLKS_MCK8 (1<<0)
919 #define AT91_TC_CMR_CLKS_MCK32 (2<<0)
920 #define AT91_TC_CMR_CLKS_MCK128 (3<<0)
921 #define AT91_TC_CMR_CLKS_MCK1024 (4<<0)
922 #define AT91_TC_CMR_CLKS_XC0 (5<<0)
923 #define AT91_TC_CMR_CLKS_XC1 (6<<0)
924 #define AT91_TC_CMR_CLKS_XC2 (7<<0)
925 #define AT91_TC_CMR_CLKI (1<<3)
926 #define AT91_TC_CMR_BURST_NONE (0<<4)
927 #define AT91_TC_CMR_BURST_XC0 (1<<4)
928 #define AT91_TC_CMR_BURST_XC1 (2<<4)
929 #define AT91_TC_CMR_BURST_XC2 (3<<4)
930 // Capture mode definitions
931 #define AT91_TC_CMR_LDBSTOP (1<<6)
932 #define AT91_TC_CMR_LDBDIS (1<<7)
933 #define AT91_TC_CMR_TRIG_NONE (0<<8)
934 #define AT91_TC_CMR_TRIG_NEG (1<<8)
935 #define AT91_TC_CMR_TRIG_POS (2<<8)
936 #define AT91_TC_CMR_TRIG_BOTH (3<<8)
937 #define AT91_TC_CMR_EXT_TRIG_TIOB (0<<10)
938 #define AT91_TC_CMR_EXT_TRIG_TIOA (1<<10)
939 #define AT91_TC_CMR_CPCTRG (1<<14)
940 #define AT91_TC_CMR_LDRA_NONE (0<<16)
941 #define AT91_TC_CMR_LDRA_TIOA_NEG (1<<16)
942 #define AT91_TC_CMR_LDRA_TIOA_POS (2<<16)
943 #define AT91_TC_CMR_LDRA_TIOA_BOTH (3<<16)
944 #define AT91_TC_CMR_LDRB_NONE (0<<18)
945 #define AT91_TC_CMR_LDRB_TIOA_NEG (1<<18)
946 #define AT91_TC_CMR_LDRB_TIOA_POS (2<<18)
947 #define AT91_TC_CMR_LDRB_TIOA_BOTH (3<<18)
948 // Waveform mode definitions
949 #define AT91_TC_CMR_CPCSTOP (1<<6)
950 #define AT91_TC_CMR_CPCDIS (1<<7)
951 #define AT91_TC_CMR_EEVTEDG_NONE (0<<8)
952 #define AT91_TC_CMR_EEVTEDG_NEG (1<<8)
953 #define AT91_TC_CMR_EEVTEDG_POS (2<<8)
954 #define AT91_TC_CMR_EEVTEDG_BOTH (3<<8)
955 #define AT91_TC_CMR_EEVT_TIOB (0<<10)
956 #define AT91_TC_CMR_EEVT_XC0 (1<<10)
957 #define AT91_TC_CMR_EEVT_XC1 (2<<10)
958 #define AT91_TC_CMR_EEVT_XC2 (3<<10)
959 #define AT91_TC_CMR_ENETRG (1<<12)
960 #define AT91_TC_CMR_CPCTRG (1<<14)
961 #define AT91_TC_CMR_WAVE (1<<15)
962 #define AT91_TC_CMR_ACPA_NONE (0<<16)
963 #define AT91_TC_CMR_ACPA_SET (1<<16)
964 #define AT91_TC_CMR_ACPA_CLEAR (2<<16)
965 #define AT91_TC_CMR_ACPA_TOGGLE (3<<16)
966 #define AT91_TC_CMR_ACPC_NONE (0<<18)
967 #define AT91_TC_CMR_ACPC_SET (1<<18)
968 #define AT91_TC_CMR_ACPC_CLEAR (2<<18)
969 #define AT91_TC_CMR_ACPC_TOGGLE (3<<18)
970 #define AT91_TC_CMR_AEEVT_NONE (0<<20)
971 #define AT91_TC_CMR_AEEVT_SET (1<<20)
972 #define AT91_TC_CMR_AEEVT_CLEAR (2<<20)
973 #define AT91_TC_CMR_AEEVT_TOGGLE (3<<20)
974 #define AT91_TC_CMR_ASWTRG_NONE (0<<22)
975 #define AT91_TC_CMR_ASWTRG_SET (1<<22)
976 #define AT91_TC_CMR_ASWTRG_CLEAR (2<<22)
977 #define AT91_TC_CMR_ASWTRG_TOGGLE (3<<22)
978 #define AT91_TC_CMR_BCPB_NONE (0<<24)
979 #define AT91_TC_CMR_BCPB_SET (1<<24)
980 #define AT91_TC_CMR_BCPB_CLEAR (2<<24)
981 #define AT91_TC_CMR_BCPB_TOGGLE (3<<24)
982 #define AT91_TC_CMR_BCPC_NONE (0<<26)
983 #define AT91_TC_CMR_BCPC_SET (1<<26)
984 #define AT91_TC_CMR_BCPC_CLEAR (2<<26)
985 #define AT91_TC_CMR_BCPC_TOGGLE (3<<26)
986 #define AT91_TC_CMR_BEEVT_NONE (0<<28)
987 #define AT91_TC_CMR_BEEVT_SET (1<<28)
988 #define AT91_TC_CMR_BEEVT_CLEAR (2<<28)
989 #define AT91_TC_CMR_BEEVT_TOGGLE (3<<28)
990 #define AT91_TC_CMR_BSWTRG_NONE (0<<30)
991 #define AT91_TC_CMR_BSWTRG_SET (1<<30)
992 #define AT91_TC_CMR_BSWTRG_CLEAR (2<<30)
993 #define AT91_TC_CMR_BSWTRG_TOGGLE (3<<30)
995 #define AT91_TC_CV 0x10
996 #define AT91_TC_RA 0x14
997 #define AT91_TC_RB 0x18
998 #define AT91_TC_RC 0x1C
999 #define AT91_TC_SR 0x20
1000 #define AT91_TC_SR_COVF (1<<0) // Counter overrun
1001 #define AT91_TC_SR_LOVR (1<<1) // Load overrun
1002 #define AT91_TC_SR_CPA (1<<2) // RA compare
1003 #define AT91_TC_SR_CPB (1<<3) // RB compare
1004 #define AT91_TC_SR_CPC (1<<4) // RC compare
1005 #define AT91_TC_SR_LDRA (1<<5) // Load A status
1006 #define AT91_TC_SR_LDRB (1<<6) // Load B status
1007 #define AT91_TC_SR_EXT (1<<7) // External trigger
1008 #define AT91_TC_SR_CLKSTA (1<<16) // Clock enable/disable status
1009 #define AT91_TC_SR_MTIOA (1<<17) // TIOA mirror
1010 #define AT91_TC_SR_MTIOB (1<<18) // TIOB mirror
1011 #define AT91_TC_IER 0x24
1012 #define AT91_TC_IER_COVF (1<<0) // Counter overrun
1013 #define AT91_TC_IER_LOVR (1<<1) // Load overrun
1014 #define AT91_TC_IER_CPA (1<<2) // RA compare
1015 #define AT91_TC_IER_CPB (1<<3) // RB compare
1016 #define AT91_TC_IER_CPC (1<<4) // RC compare
1017 #define AT91_TC_IER_LDRA (1<<5) // Load A status
1018 #define AT91_TC_IER_LDRB (1<<6) // Load B status
1019 #define AT91_TC_IER_EXT (1<<7) // External trigger
1020 #define AT91_TC_IDR 0x28
1021 #define AT91_TC_IMR 0x2C
1022 #define AT91_TC_TC1 0x40
1023 #define AT91_TC_TC2 0x80
1024 #define AT91_TC_BCR 0xC0
1025 #define AT91_TC_BCR_SYNC 0x01
1026 #define AT91_TC_BMR 0xC4
1027 #define AT91_TC_BMR_MASK (0x3f)
1028 #define AT91_TC_BMR_TC0XC0S_TCLK0 (0 << 0) // XC0S = TCLK0
1029 #define AT91_TC_BMR_TC0XC0S_NONE (1 << 0) // XC0S = none
1030 #define AT91_TC_BMR_TC0XC0S_TIOA1 (2 << 0) // XC0S = TIOA1
1031 #define AT91_TC_BMR_TC0XC0S_TIOA2 (3 << 0) // XC0S = TIOA2
1032 #define AT91_TC_BMR_TC1XC1S_TCLK1 (0 << 2) // XC1S = TCLK1
1033 #define AT91_TC_BMR_TC1XC1S_NONE (1 << 2) // XC1S = none
1034 #define AT91_TC_BMR_TC1XC1S_TIOA0 (2 << 2) // XC1S = TIOA0
1035 #define AT91_TC_BMR_TC1XC1S_TIOA2 (3 << 2) // XC1S = TIOA2
1036 #define AT91_TC_BMR_TC2XC2S_TCLK2 (0 << 4) // XC2S = TCLK2
1037 #define AT91_TC_BMR_TC2XC2S_NONE (1 << 4) // XC2S = none
1038 #define AT91_TC_BMR_TC2XC2S_TIOA0 (2 << 4) // XC2S = TIOA0
1039 #define AT91_TC_BMR_TC2XC2S_TIOA1 (3 << 4) // XC2S = TIOA1
1043 //=============================================================================
1044 // External Bus Interface
1047 #define AT91_EBI 0xFFE00000
1050 #define AT91_EBI_CSR0 0x00
1051 #define AT91_EBI_CSR1 0x04
1052 #define AT91_EBI_CSR2 0x08
1053 #define AT91_EBI_CSR3 0x0C
1054 #define AT91_EBI_CSR4 0x10
1055 #define AT91_EBI_CSR5 0x14
1056 #define AT91_EBI_CSR6 0x18
1057 #define AT91_EBI_CSR7 0x1C // Chip select
1058 #define AT91_EBI_CSR_DBW_16 0x1 // Data bus 16 bits wide
1059 #define AT91_EBI_CSR_DBW_8 0x2 // Data bus 8 bits wide
1060 #define AT91_EBI_CSR_NWS_1 (0x0 << 2)
1061 #define AT91_EBI_CSR_NWS_2 (0x1 << 2)
1062 #define AT91_EBI_CSR_NWS_3 (0x2 << 2)
1063 #define AT91_EBI_CSR_NWS_4 (0x3 << 2)
1064 #define AT91_EBI_CSR_NWS_5 (0x4 << 2)
1065 #define AT91_EBI_CSR_NWS_6 (0x5 << 2)
1066 #define AT91_EBI_CSR_NWS_7 (0x6 << 2)
1067 #define AT91_EBI_CSR_NWS_8 (0x7 << 2) // Number of wait states
1068 #define AT91_EBI_CSR_WSE (0x1 << 5) // Wait state enable
1069 #define AT91_EBI_CSR_PAGES_1M (0x0 << 7)
1070 #define AT91_EBI_CSR_PAGES_4M (0x1 << 7)
1071 #define AT91_EBI_CSR_PAGES_16M (0x2 << 7)
1072 #define AT91_EBI_CSR_PAGES_64M (0x3 << 7) // Page size
1073 #define AT91_EBI_CSR_TDF_0 (0x0 << 9)
1074 #define AT91_EBI_CSR_TDF_1 (0x1 << 9)
1075 #define AT91_EBI_CSR_TDF_2 (0x2 << 9)
1076 #define AT91_EBI_CSR_TDF_3 (0x3 << 9)
1077 #define AT91_EBI_CSR_TDF_4 (0x4 << 9)
1078 #define AT91_EBI_CSR_TDF_5 (0x5 << 9)
1079 #define AT91_EBI_CSR_TDF_6 (0x6 << 9)
1080 #define AT91_EBI_CSR_TDF_7 (0x7 << 9) // Data float output time
1081 #define AT91_EBI_CSR_BAT (0x1 << 12) // Byte access type
1082 #define AT91_EBI_CSR_CSEN (0x1 << 13) // Chip select enable
1083 #define AT91_EBI_CSR_BA (0xFFF << 20) // Base address
1084 #define AT91_EBI_RCR 0x20 // Reset control
1085 #define AT91_EBI_RCR_RCB 0x1 // Remap command bit
1086 #define AT91_EBI_MCR 0x24 // Memory control
1087 #define AT91_EBI_MCR_ALE_16M 0x0
1088 #define AT91_EBI_MCR_ALE_8M 0x4
1089 #define AT91_EBI_MCR_ALE_4M 0x5
1090 #define AT91_EBI_MCR_ALE_2M 0x6
1091 #define AT91_EBI_MCR_ALE_1M 0x7 // Address line enable
1092 #define AT91_EBI_MCR_DRP (0x1 << 4) // Data read protocol
1094 //=============================================================================
1095 // Power Saving or Management
1097 #if defined(CYGHWR_HAL_ARM_AT91_R40807) || \
1098 defined(CYGHWR_HAL_ARM_AT91_R40008)
1103 #define AT91_PS 0xFFFF4000
1106 #define AT91_PS_CR 0x000 // Control
1107 #define AT91_PS_CR_CPU (1<<0) // Disable CPU clock (idle mode)
1108 #define AT91_PS_PCER 0x004 // Peripheral clock enable
1109 #define AT91_PS_PCDR 0x008 // Peripheral clock disable
1110 #define AT91_PS_PCSR 0x00c // Peripheral clock status
1112 #elif defined(CYGHWR_HAL_ARM_AT91_M42800A) || \
1113 defined(CYGHWR_HAL_ARM_AT91_M55800A) || \
1114 defined(CYGHWR_HAL_ARM_AT91SAM7)
1116 // (Advanced) Power Management
1119 #define AT91_PMC 0xFFFF4000
1122 #define AT91_PMC_SCER 0x00
1123 #define AT91_PMC_SCDR 0x04
1124 #define AT91_PMC_SCSR 0x08
1126 #define AT91_PMC_PCER 0x10
1127 #define AT91_PMC_PCDR 0x14
1128 #define AT91_PMC_PCSR 0x18
1130 #define AT91_PMC_CGMR 0x20
1133 #define AT91_PMC_SR 0x30
1136 #ifndef AT91_PMC_IER
1137 #define AT91_PMC_IER 0x34
1140 #ifndef AT91_PMC_IDR
1141 #define AT91_PMC_IDR 0x38
1144 #ifndef AT91_PMC_IMR
1145 #define AT91_PMC_IMR 0x3c
1148 #if defined(CYGHWR_HAL_ARM_AT91_M42800A)
1150 #define AT91_PMC_PCER_US0 (1<<2)
1151 #define AT91_PMC_PCER_US1 (1<<3)
1152 #define AT91_PMC_PCER_SPIA (1<<4)
1153 #define AT91_PMC_PCER_SPIB (1<<5)
1154 #define AT91_PMC_PCER_TC0 (1<<6)
1155 #define AT91_PMC_PCER_TC1 (1<<7)
1156 #define AT91_PMC_PCER_TC2 (1<<8)
1157 #define AT91_PMC_PCER_TC3 (1<<9)
1158 #define AT91_PMC_PCER_TC4 (1<<10)
1159 #define AT91_PMC_PCER_TC5 (1<<11)
1160 #define AT91_PMC_PCER_PIOA (1<<13)
1161 #define AT91_PMC_PCER_PIOB (1<<14)
1163 #define AT91_PMC_CGMR_PRES_NONE 0
1164 #define AT91_PMC_CGMR_PRES_DIV2 1
1165 #define AT91_PMC_CGMR_PRES_DIV4 2
1166 #define AT91_PMC_CGMR_PRES_DIV8 3
1167 #define AT91_PMC_CGMR_PRES_DIV16 4
1168 #define AT91_PMC_CGMR_PRES_DIV32 5
1169 #define AT91_PMC_CGMR_PRES_DIV64 6
1170 #define AT91_PMC_CGMR_PRES_RES 7
1171 #define AT91_PMC_CGMR_PLLA 0x00
1172 #define AT91_PMC_CGMR_PLLB 0x08
1173 #define AT91_PMC_CGMR_MCK_SLCK (0<<4)
1174 #define AT91_PMC_CGMR_MCK_MCK (1<<4)
1175 #define AT91_PMC_CGMR_MCK_MCKINV (2<<4)
1176 #define AT91_PMC_CGMR_MCK_MCKD2 (3<<4)
1177 #define AT91_PMC_CGMR_MCKO_ENA (0<<6)
1178 #define AT91_PMC_CGMR_MCKO_DIS (1<<6)
1179 #define AT91_PMC_CGMR_CSS_SLCK (0<<7)
1180 #define AT91_PMC_CGMR_CSS_PLL (1<<7)
1182 #define AT91_PMC_CGMR_PLL_MUL(x) ((x)<<8)
1183 #define AT91_PMC_CGMR_PLL_CNT(x) ((x)<<24)
1185 #define AT91_PMC_SR_LOCK 0x01
1187 #elif defined(CYGHWR_HAL_ARM_AT91_M55800A)
1189 #define AT91_PMC_PCER_US0 (1<<2)
1190 #define AT91_PMC_PCER_US1 (1<<3)
1191 #define AT91_PMC_PCER_US2 (1<<4)
1192 #define AT91_PMC_PCER_SPI (1<<5)
1193 #define AT91_PMC_PCER_TC0 (1<<6)
1194 #define AT91_PMC_PCER_TC1 (1<<7)
1195 #define AT91_PMC_PCER_TC2 (1<<8)
1196 #define AT91_PMC_PCER_TC3 (1<<9)
1197 #define AT91_PMC_PCER_TC4 (1<<10)
1198 #define AT91_PMC_PCER_TC5 (1<<11)
1199 #define AT91_PMC_PCER_PIOA (1<<13)
1200 #define AT91_PMC_PCER_PIOB (1<<14)
1201 #define AT91_PMC_PCER_ADC0 (1<<15)
1202 #define AT91_PMC_PCER_ADC1 (1<<16)
1203 #define AT91_PMC_PCER_DAC0 (1<<17)
1204 #define AT91_PMC_PCER_DAC1 (1<<18)
1206 #define AT91_PMC_CGMR_MOSC_XTAL 0
1207 #define AT91_PMC_CGMR_MOSC_BYP 1
1208 #define AT91_PMC_CGMR_MOSC_DIS (0<<1)
1209 #define AT91_PMC_CGMR_MOSC_ENA (1<<1)
1210 #define AT91_PMC_CGMR_MCKO_ENA (0<<2)
1211 #define AT91_PMC_CGMR_MCKO_DIS (1<<2)
1212 #define AT91_PMC_CGMR_PRES_NONE (0<<4)
1213 #define AT91_PMC_CGMR_PRES_DIV2 (1<<4)
1214 #define AT91_PMC_CGMR_PRES_DIV4 (2<<4)
1215 #define AT91_PMC_CGMR_PRES_DIV8 (3<<4)
1216 #define AT91_PMC_CGMR_PRES_DIV16 (4<<4)
1217 #define AT91_PMC_CGMR_PRES_DIV32 (5<<4)
1218 #define AT91_PMC_CGMR_PRES_DIV64 (6<<4)
1219 #define AT91_PMC_CGMR_PRES_RES (7<<4)
1220 #define AT91_PMC_CGMR_CSS_LF (0<<14)
1221 #define AT91_PMC_CGMR_CSS_MOSC (1<<14)
1222 #define AT91_PMC_CGMR_CSS_PLL (2<<14)
1223 #define AT91_PMC_CGMR_CSS_RES (3<<14)
1225 #define AT91_PMC_CGMR_PLL_MUL(x) ((x)<<8)
1226 #define AT91_PMC_CGMR_OSC_CNT(x) ((x)<<16)
1227 #define AT91_PMC_CGMR_PLL_CNT(x) ((x)<<24)
1229 #define AT91_PMC_PCR 0x28
1230 #define AT91_PMC_PCR_SHDALC 1
1231 #define AT91_PMC_PCR_WKACKC 2
1233 #define AT91_PMC_PMR 0x2c
1234 #define AT91_PMC_PMR_SHDALS_TRI 0
1235 #define AT91_PMC_PMR_SHDALS_LEVEL0 1
1236 #define AT91_PMC_PMR_SHDALS_LEVEL1 2
1237 #define AT91_PMC_PMR_SHDALS_RES 3
1238 #define AT91_PMC_PMR_WKACKS_TRI (0<<2)
1239 #define AT91_PMC_PMR_WKACKS_LEVEL0 (1<<2)
1240 #define AT91_PMC_PMR_WKACKS_LEVEL1 (2<<2)
1241 #define AT91_PMC_PMR_WKACKS_RES (3<<2)
1242 #define AT91_PMC_PMR_ALWKEN (1<<4)
1243 #define AT91_PMC_PMR_ALSHEN (1<<5)
1245 #define AT91_PMC_PMR_WKEDG_NONE (0<<6)
1246 #define AT91_PMC_PMR_WKEDG_POS (1<<6)
1247 #define AT91_PMC_PMR_WKEDG_NEG (2<<6)
1248 #define AT91_PMC_PMR_WKEDG_BOTH (3<<6)
1250 #define AT91_PMC_SR_MOSCS 0x01
1251 #define AT91_PMC_SR_LOCK 0x02
1253 #elif defined(CYGHWR_HAL_ARM_AT91_JTST)
1254 // No power management control for the JTST
1256 #elif defined(CYGHWR_HAL_ARM_AT91SAM7S)
1257 #define AT91_PMC_SCER_PCK (1 << 0) // Processor Clock
1258 #define AT91_PMC_SCER_UDP (1 << 7) // USB Device Clock
1259 #define AT91_PMC_SCER_PCK0 (1 << 8) // Programmable Clock Output
1260 #define AT91_PMC_SCER_PCK1 (1 << 9) // Programmable Clock Output
1261 #define AT91_PMC_SCER_PCK2 (1 << 10) // Programmable Clock Output
1262 #define AT91_PMC_SCER_PCK3 (1 << 11) // Programmable Clock Output
1264 #define AT91_PMC_PCER_PIOA (1 << 2) // Parallel IO Controller
1265 #define AT91_PMC_PCER_ADC (1 << 4) // Analog-to-Digital Conveter
1266 #define AT91_PMC_PCER_SPI (1 << 5) // Serial Peripheral Interface
1267 #define AT91_PMC_PCER_US0 (1 << 6) // USART 0
1268 #define AT91_PMC_PCER_US1 (1 << 7) // USART 1
1269 #define AT91_PMC_PCER_SSC (1 << 8) // Serial Synchronous Controller
1270 #define AT91_PMC_PCER_TWI (1 << 9) // Two-Wire Interface
1271 #define AT91_PMC_PCER_PWMC (1 <<10) // PWM Controller
1272 #define AT91_PMC_PCER_UDP (1 <<11) // USB Device Port
1273 #define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0
1274 #define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1
1275 #define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2
1277 #elif defined(CYGHWR_HAL_ARM_AT91SAM7X)
1278 #define AT91_PMC_SCER_PCK (1 << 0) // Processor Clock
1279 #define AT91_PMC_SCER_UDP (1 << 7) // USB Device Clock
1280 #define AT91_PMC_SCER_PCK0 (1 << 8) // Programmable Clock Output
1281 #define AT91_PMC_SCER_PCK1 (1 << 9) // Programmable Clock Output
1282 #define AT91_PMC_SCER_PCK2 (1 << 10) // Programmable Clock Output
1283 #define AT91_PMC_SCER_PCK3 (1 << 11) // Programmable Clock Output
1285 #define AT91_PMC_PCER_PIOA (1 << 2) // Parallel IO Controller
1286 #define AT91_PMC_PCER_PIOB (1 << 3) // Parallel IO Controller
1287 #define AT91_PMC_PCER_SPI (1 << 4) // Serial Peripheral Interface
1288 #define AT91_PMC_PCER_SPI1 (1 << 5) // Serial Peripheral Interface
1289 #define AT91_PMC_PCER_US0 (1 << 6) // USART 0
1290 #define AT91_PMC_PCER_US1 (1 << 7) // USART 1
1291 #define AT91_PMC_PCER_SSC (1 << 8) // Serial Synchronous Controller
1292 #define AT91_PMC_PCER_TWI (1 << 9) // Two-Wire Interface
1293 #define AT91_PMC_PCER_PWMC (1 <<10) // PWM Controller
1294 #define AT91_PMC_PCER_UDP (1 <<11) // USB Device Port
1295 #define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0
1296 #define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1
1297 #define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2
1298 #define AT91_PMC_PCER_CAN (1 <<15) // Controller Area Network
1299 #define AT91_PMC_PCER_EMAC (1 <<16) // Ethernet MAC
1300 #define AT91_PMC_PCER_ADC (1 <<17) // Analog-to-Digital Conveter
1301 #else // Something unknown
1303 #error Unknown AT91 variant
1308 //=============================================================================
1312 #define AT91_WD 0xFFFF8000
1315 #define AT91_WD_OMR 0x00
1316 #define AT91_WD_OMR_WDEN 0x00000001
1317 #define AT91_WD_OMR_RSTEN 0x00000002
1318 #define AT91_WD_OMR_IRQEN 0x00000004
1319 #define AT91_WD_OMR_EXTEN 0x00000008
1320 #define AT91_WD_OMR_OKEY (0x00000234 << 4)
1321 #define AT91_WD_CMR 0x04
1322 #define AT91_WD_CMR_WDCLKS 0x00000003
1323 #define AT91_WD_CMR_HPCV 0x0000003C
1324 #define AT91_WD_CMR_CKEY (0x0000006E << 7)
1325 #define AT91_WD_CR 0x08
1326 #define AT91_WD_CR_RSTKEY 0x0000C071
1327 #define AT91_WD_SR 0x0C
1328 #define AT91_WD_SR_WDOVF 0x00000001
1330 //=============================================================================
1334 #define AT91_SPI 0xFFFBC000
1337 #define AT91_SPI_CR 0x00 // Control Register
1338 #define AT91_SPI_CR_SPIEN 0x00000001 // SPI Enable
1339 #define AT91_SPI_CR_SPIDIS 0x00000002 // SPI Disable
1340 #define AT91_SPI_CR_SWRST 0x00000080 // SPI Software reset
1341 #define AT91_SPI_MR 0x04 // Mode Register
1342 #define AT91_SPI_MR_MSTR 0x00000001 // Master/Slave Mode
1343 #define AT91_SPI_MR_PS 0x00000002 // Peripheral Select
1344 #define AT91_SPI_MR_PCSDEC 0x00000004 // Chip Select Decode
1345 #define AT91_SPI_MR_DIV32 0x00000008 // Clock Selection
1346 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
1347 #define AT91_SPI_MR_MODFDIS (1<<4) // Mode Failure Detect Disable
1349 #define AT91_SPI_MR_LLB 0x00000080 // Local Loopback Enable
1350 #define AT91_SPI_MR_PCS(x) (((x)&0x0F)<<16) // Peripheral Chip Select
1351 #define AT91_SPI_MR_DLYBCS(x) (((x)&0xFF)<<24) // Delay Between Chip Selects
1352 #define AT91_SPI_RDR 0x08 // Receive Data Register
1353 #define AT91_SPI_TDR 0x0C // Transmit Data Register
1354 #define AT91_SPI_SR 0x10 // Status Register
1355 #define AT91_SPI_SR_RDRF 0x00000001 // Receive Data Register Full
1356 #define AT91_SPI_SR_TDRE 0x00000002 // Tx Data Register Empty
1357 #define AT91_SPI_SR_MODF 0x00000004 // Mode Fault Error
1358 #define AT91_SPI_SR_OVRES 0x00000008 // Overrun Error Status
1359 #define AT91_SPI_SR_ENDRX 0x00000010 // End of Receiver Transfer
1360 #define AT91_SPI_SR_ENDTX 0x00000020 // End of Transmitter Transfer
1361 #define AT91_SPI_SR_SPIENS 0x00010000 // SPI Enable Status
1362 #define AT91_SPI_IER 0x14 // Interrupt Enable Register
1363 #define AT91_SPI_IDR 0x18 // Interrupt Disable Register
1364 #define AT91_SPI_IMR 0x1C // Interrupt Mask Register
1365 // DMA registers are PDC registers
1366 // can be different from target to target
1367 #ifndef AT91_SPI_RPR
1368 #define AT91_SPI_RPR 0x20 // Receive Pointer Register
1370 #ifndef AT91_SPI_RCR
1371 #define AT91_SPI_RCR 0x24 // Receive Counter Register
1373 #ifndef AT91_SPI_TPR
1374 #define AT91_SPI_TPR 0x28 // Transmit Pointer Register
1376 #ifndef AT91_SPI_TCR
1377 #define AT91_SPI_TCR 0x2C // Transmit Counter Register
1380 // PDC Control register bits
1381 #define AT91_SPI_PTCR_RXTEN (1 << 0)
1382 #define AT91_SPI_PTCR_RXTDIS (1 << 1)
1383 #define AT91_SPI_PTCR_TXTEN (1 << 8)
1384 #define AT91_SPI_PTCR_TXTDIS (1 << 9)
1386 #define AT91_SPI_CSR0 0x30 // Chip Select Register 0
1387 #define AT91_SPI_CSR1 0x34 // Chip Select Register 1
1388 #define AT91_SPI_CSR2 0x38 // Chip Select Register 2
1389 #define AT91_SPI_CSR3 0x3C // Chip Select Register 3
1390 #define AT91_SPI_CSR_CPOL 0x00000001 // Clock Polarity
1391 #define AT91_SPI_CSR_NCPHA 0x00000002 // Clock Phase
1392 #define AT91_SPI_CSR_BITS(x) (((x)&0x0F)<<4) // Bits Per Transfer
1393 #define AT91_SPI_CSR_BITS8 AT91_SPI_CSR_BITS(0)
1394 #define AT91_SPI_CSR_BITS9 AT91_SPI_CSR_BITS(1)
1395 #define AT91_SPI_CSR_BITS10 AT91_SPI_CSR_BITS(2)
1396 #define AT91_SPI_CSR_BITS11 AT91_SPI_CSR_BITS(3)
1397 #define AT91_SPI_CSR_BITS12 AT91_SPI_CSR_BITS(4)
1398 #define AT91_SPI_CSR_BITS13 AT91_SPI_CSR_BITS(5)
1399 #define AT91_SPI_CSR_BITS14 AT91_SPI_CSR_BITS(6)
1400 #define AT91_SPI_CSR_BITS15 AT91_SPI_CSR_BITS(7)
1401 #define AT91_SPI_CSR_BITS16 AT91_SPI_CSR_BITS(8)
1402 #define AT91_SPI_CSR_SCBR(x) (((x)&0xFF)<<8) // Serial Clock Baud Rate
1403 #define AT91_SPI_CSR_DLYBS(x) (((x)&0xFF)<<16) // Delay Before SPCK
1404 #define AT91_SPI_CSR_DLYBCT(x) (((x)&0xFF)<<24) // Delay Between two transfers
1406 //=============================================================================
1407 // Watchdog Timer Controller
1409 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
1412 #define AT91_WDTC 0xFFFFFD40
1415 #define AT91_WDTC_WDCR 0x00 // Watchdog Control Register
1416 #define AT91_WDTC_WDCR_RELOAD (1 << 0) // Reload the watchdog
1417 #define AT91_WDTC_WDCR_KEY (0xa5 << 24) // Password for the write op
1418 #define AT91_WDTC_WDMR 0x04 // Watchdog Mode Register
1419 #define AT91_WDTC_WDMR_FIEN (1 << 12) // Fault Interrupt Mode Enable
1420 #define AT91_WDTC_WDMR_RSTEN (1 << 13) // Reset Enable
1421 #define AT91_WDTC_WDMR_RPROC (1 << 14) // Trigger a processor reset
1422 #define AT91_WDTC_WDMR_DIS (1 << 15) // Disable
1423 #define AT91_WDTC_WDMR_WDD_SHIFT (16) // Delta Value shift
1424 #define AT91_WDTC_WDMR_DBGHLT (1 << 28) // Stop when in debug state
1425 #define AT91_WDTC_WDMR_IDLEHLT (1 << 29) // Stop when in idle more
1426 #define AT91_WDTC_WDSR 0x08 // Watchdog Status Register
1427 #define AT91_WDTC_WDSR_UNDER (1 << 0) // Underflow has occurred
1428 #define AT91_WDTC_WDSR_ERROR (1 << 1) // Error has occurred
1429 #endif //CYGHWR_HAL_ARM_AT91SAM7
1431 //=============================================================================
1434 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
1437 #define AT91_RST 0xFFFFFD00
1440 #define AT91_RST_RCR 0x00 // Reset Control Register
1441 #define AT91_RST_RCR_PROCRST (1 << 0) // Processor Reset
1442 #define AT91_RST_RCR_ICERST (1 << 1) // ICE Reset
1443 #define AT91_RST_RCR_PERRST (1 << 2) // Peripheral Reset
1444 #define AT91_RST_RCR_EXTRST (1 << 3) // External Reset
1445 #define AT91_RST_RCR_KEY (0xA5 << 24) // Key
1446 #define AT91_RST_RSR 0x04 // Reset Status Register
1447 #define AT91_RST_RSR_USER (1 << 0) // User Reset
1448 #define AT91_RST_RSR_BROWN (1 << 1) // Brownout detected
1449 #define AT91_RST_RSR_TYPE_POWERUP (0 << 8) // Power on Reset
1450 #define AT91_RST_RSR_TYPE_WATCHDOG (2 << 8) // Watchdog Reset
1451 #define AT91_RST_RSR_TYPE_SW (3 << 8) // Software Reset
1452 #define AT91_RST_RSR_TYPE_USER (4 << 8) // NRST pin Reset
1453 #define AT91_RST_RSR_TYPE_BROWNOUT (5 << 8) // Brown-out Reset
1454 #define AT91_RST_RSR_NRST_SET (1 << 16) // NRST pin set
1455 #define AT91_RST_RSR_SRCMP (1 << 17) // Software reset in progress
1456 #define AT91_RST_RMR 0x08 // Reset Mode Register
1457 #define AT91_RST_RMR_URSTEN (1 << 0) // User Reset Enabled
1458 #define AT91_RST_RMR_URSTIEN (1 << 4) // User Reset Interrupt Enabled
1459 #define AT91_RST_RMR_BODIEN (1 << 16) // Brownout Dection Interrupt Enabled
1460 #define AT91_RST_RMR_KEY (0xA5 << 24) // Key
1464 //=============================================================================
1465 // Memory Controller
1467 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
1470 #define AT91_MC 0xFFFFFF00
1473 #define AT91_MC_RCR 0x00 // Remap Control Register
1474 #define AT91_MC_ASR 0x04 // Abort Status Register
1475 #define AT91_MC_AASR 0x08 // Abort Address Status Register
1476 #define AT91_MC_FMR 0x60 // Flash Mode Register
1477 #define AT91_MC_FMR_FRDY (1 << 0) // Enable interrupt for Flash Ready
1478 #define AT91_MC_FMR_LOCKE (1 << 2) // Enable interrupt for Flash Lock Error
1479 #define AT91_MC_FMR_PROGE (1 << 3) // Enable interrupt for Flash Prog Error
1480 #define AT91_MC_FMR_NEBP (1 << 7) // No erase before programming
1481 #define AT91_MC_FMR_0FWS (0 << 8) // 1R,2W wait states
1482 #define AT91_MC_FMR_1FWS (1 << 8) // 2R,3W wait states
1483 #define AT91_MC_FMR_2FWS (2 << 8) // 3R,4W wait states
1484 #define AT91_MC_FMR_3FWS (3 << 8) // 4R,4W wait states
1485 #define AT91_MC_FMR_FMCN_MASK (0xff << 16)
1486 #define AT91_MC_FMR_FMCN_SHIFT 16
1487 #define AT91_MC_FCR 0x64 // Flash Command Register
1488 #define AT91_MC_FCR_START_PROG (0x1 << 0) // Start Programming of Page
1489 #define AT91_MC_FCR_LOCK (0x2 << 0) // Lock sector
1490 #define AT91_MC_FCR_PROG_LOCK (0x3 << 0) // Program and Lock
1491 #define AT91_MC_FCR_UNLOCK (0x4 << 0) // Unlock a segment
1492 #define AT91_MC_FCR_ERASE_ALL (0x8 << 0) // Erase everything
1493 #define AT91_MC_FCR_SET_GP_NVM (0xb << 0) // Set general purpose NVM bits
1494 #define AT91_MC_FCR_CLR_GP_NVM (0xd << 0) // Clear general purpose NVM bits
1495 #define AT91_MC_FCR_SET_SECURITY (0xf << 0) // Set security bit
1496 #define AT91_MC_FCR_PAGE_MASK (0x3ff)
1497 #define AT91_MC_FCR_PAGE_SHIFT 8
1498 #define AT91_MC_FCR_KEY (0x5a << 24) // Key to enable command
1499 #define AT91_MC_FSR 0x68 // Flash Status Register
1500 #define AT91_MC_FSR_FRDY (1 << 0) // Flash Ready for next command
1501 #define AT91_MC_FSR_LOCKE (1 << 2) // Programming of a locked block
1502 #define AT91_MC_FSR_PROGE (1 << 3) // Programming error
1503 #define AT91_MC_FSR_SECURITY (1 << 4) // Security bit is set
1504 #define AT91_MC_FSR_GPNVM0 (1 << 8) // General purpose NVM bit 0
1505 #define AT91_MC_FSR_GPNVM1 (1 << 9) // General purpose NVM bit 1
1508 //=============================================================================
1511 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
1514 #define AT91_DBG 0xFFFFF200
1517 #define AT91_DBG_CR 0x00 // Control Register
1518 #define AT91_DBG_CR_RSTRX (0x1 << 2) // Reset Receiver
1519 #define AT91_DBG_CR_RSTTX (0x1 << 3) // Reset Transmitter
1520 #define AT91_DBG_CR_RXEN (0x1 << 4) // Receiver Enable
1521 #define AT91_DBG_CR_RXDIS (0x1 << 5) // Receiver Disable
1522 #define AT91_DBG_CR_TXEN (0x1 << 6) // Transmitter Enable
1523 #define AT91_DBG_CR_TXDIS (0x1 << 7) // Transmitter Disable
1524 #define AT91_DBG_CR_RSTSTA (0x1 << 8) // Reset Status Bits
1525 #define AT91_DBG_MR 0x04 // Mode Register
1526 #define AT91_DBG_MR_PAR_EVEN (0x0 << 9) // Even Parity
1527 #define AT91_DBG_MR_PAR_ODD (0x1 << 9) // Odd Parity
1528 #define AT91_DBG_MR_PAR_SPACE (0x2 << 9) // Parity forced to Space
1529 #define AT91_DBG_MR_PAR_MARK (0x3 << 9) // Parity forced to Mark
1530 #define AT91_DBG_MR_PAR_NONE (0x4 << 9) // No Parity
1531 #define AT91_DBG_MR_PAR_MULTI (0x6 << 9) // Multi-drop mode
1532 #define AT91_DBG_MR_CHMODE_NORMAL (0x0 << 14) // Normal mode
1533 #define AT91_DBG_MR_CHMODE_AUTO (0x1 << 14) // Automatic Echo
1534 #define AT91_DBG_MR_CHMODE_LOCAL (0x2 << 14) // Local Loopback
1535 #define AT91_DBG_MR_CHMODE_REMOTE (0x3 << 14) // Remote Loopback
1536 #define AT91_DBG_IER 0x08 // Interrupt Enable Register
1537 #define AT91_DBG_IDR 0x0c // Interrupt Disable Register
1538 #define AT91_DBG_IMR 0x10 // Interrupt Mask Register
1539 #define AT91_DBG_CSR 0x14 // Channel Status Register
1540 #define AT91_DBG_CSR_RXRDY (1 << 0) // Receiver Ready
1541 #define AT91_DBG_CSR_TXRDY (1 << 1) // Transmitter Ready
1542 #define AT91_DBG_RHR 0x18 // Receiver Holding Register
1543 #define AT91_DBG_THR 0x1c // Transmitter Holding Register
1544 #define AT91_DBG_BRGR 0x20 // Baud Rate Generator Register
1545 #define AT91_DBG_C1R 0x40 // Chip ID1 register
1546 #define AT91_DBG_C1R_ARM945ES (1 << 5)
1547 #define AT91_DBG_C1R_ARM7TDMI (2 << 5)
1548 #define AT91_DBG_C1R_ARM920T (4 << 5)
1549 #define AT91_DBG_C1R_ARM926EJ (5 << 5)
1550 #define AT91_DBG_C1R_CPU_MASK (0x7 << 5)
1551 #define AT91_DBG_C1R_FLASH_0K (0x0 << 8)
1552 #define AT91_DBG_C1R_FLASH_8K (0x1 << 8)
1553 #define AT91_DBG_C1R_FLASH_16K (0x2 << 8)
1554 #define AT91_DBG_C1R_FLASH_32K (0x3 << 8)
1555 #define AT91_DBG_C1R_FLASH_64K (0x5 << 8)
1556 #define AT91_DBG_C1R_FLASH_128K (0x7 << 8)
1557 #define AT91_DBG_C1R_FLASH_256K (0x9 << 8)
1558 #define AT91_DBG_C1R_FLASH_512K (0xa << 8)
1559 #define AT91_DBG_C1R_FLASH_1024K (0xc << 8)
1560 #define AT91_DBG_C1R_FLASH_2048K (0xe << 8)
1561 #define AT91_DBG_C1R_FLASH_MASK (0xf << 8)
1562 #define AT91_DBG_C1R_FLASH2_0K (0x0 << 12)
1563 #define AT91_DBG_C1R_FLASH2_8K (0x1 << 12)
1564 #define AT91_DBG_C1R_FLASH2_16K (0x2 << 12)
1565 #define AT91_DBG_C1R_FLASH2_32K (0x3 << 12)
1566 #define AT91_DBG_C1R_FLASH2_64K (0x5 << 12)
1567 #define AT91_DBG_C1R_FLASH2_128K (0x7 << 12)
1568 #define AT91_DBG_C1R_FLASH2_256K (0x9 << 12)
1569 #define AT91_DBG_C1R_FLASH2_512K (0xa << 12)
1570 #define AT91_DBG_C1R_FLASH2_1024K (0xc << 12)
1571 #define AT91_DBG_C1R_FLASH2_2048K (0xe << 12)
1572 #define AT91_DBG_C1R_FLASH2_MASK (0xf << 12)
1573 #define AT91_DBG_C1R_SRAM_1K (0x1 << 16)
1574 #define AT91_DBG_C1R_SRAM_2K (0x2 << 16)
1575 #define AT91_DBG_C1R_SRAM_112K (0x4 << 16)
1576 #define AT91_DBG_C1R_SRAM_4K (0x5 << 16)
1577 #define AT91_DBG_C1R_SRAM_80K (0x6 << 16)
1578 #define AT91_DBG_C1R_SRAM_160K (0x7 << 16)
1579 #define AT91_DBG_C1R_SRAM_8K (0x8 << 16)
1580 #define AT91_DBG_C1R_SRAM_16K (0x9 << 16)
1581 #define AT91_DBG_C1R_SRAM_32K (0xa << 16)
1582 #define AT91_DBG_C1R_SRAM_64K (0xb << 16)
1583 #define AT91_DBG_C1R_SRAM_128K (0xc << 16)
1584 #define AT91_DBG_C1R_SRAM_256K (0xd << 16)
1585 #define AT91_DBG_C1R_SRAM_96K (0xe << 16)
1586 #define AT91_DBG_C1R_SRAM_512K (0xf << 16)
1587 #define AT91_DBG_C1R_SRAM_MASK (0xf << 16)
1588 #define AT91_DBG_C1R_ARCH_AT75Cxx (0xf0 << 20)
1589 #define AT91_DBG_C1R_ARCH_AT91x40 (0x40 << 20)
1590 #define AT91_DBG_C1R_ARCH_AT91x63 (0x63 << 20)
1591 #define AT91_DBG_C1R_ARCH_AT91x55 (0x55 << 20)
1592 #define AT91_DBG_C1R_ARCH_AT91x42 (0x42 << 20)
1593 #define AT91_DBG_C1R_ARCH_AT91x92 (0x92 << 20)
1594 #define AT91_DBG_C1R_ARCH_AT91x34 (0x24 << 20)
1595 #define AT91_DBG_C1R_ARCH_AT91SAM7Axx (0x60 << 20)
1596 #define AT91_DBG_C1R_ARCH_AT91SAM7Sxx (0x70 << 20)
1597 #define AT91_DBG_C1R_ARCH_AT91SAM7XC (0x71 << 20)
1598 #define AT91_DBG_C1R_ARCH_AT91SAM7SExx (0x72 << 20)
1599 #define AT91_DBG_C1R_ARCH_AT91SAM7Lxx (0x73 << 20)
1600 #define AT91_DBG_C1R_ARCH_AT91SAM7Xxx (0x75 << 20)
1601 #define AT91_DBG_C1R_ARCH_AT91SAM9xx (0x19 << 20)
1602 #define AT91_DBG_C1R_ARCH_MASK (0xff << 20)
1603 #define AT91_DBG_C1R_NVPTYP_ROM (0 << 28) // ROM only
1604 #define AT91_DBG_C1R_NVPTYP_RLOCF (1 << 28) // ROMless of on chip Flash
1605 #define AT91_DBG_C1R_NVPTYP_SRAMROM (4 << 28) // SRAM emulating ROM
1606 #define AT91_DBG_C1R_NVPTYP_EFLASH (2 << 28) // Embedded Flash
1607 #define AT91_DBG_C1R_NVPTYP_ROMFLASH (3 << 28) // ROM & FLASH
1608 #define AT91_DBG_C1R_NVPTYP_MASK (7 << 28)
1609 #define AT91_DBG_C1R_EXT (1 << 31) // Extension Register Exists
1610 #define AT91_DBG_C2R 0x44 // Chip ID2 register
1611 #define AT91_DBG_FNTR 0x48 // Force NTRST Register
1612 #define AT91_DBG_RPR 0x100 // Receiver Pointer Register
1613 #define AT91_DBG_RCR 0x104 // Receiver Counter Register
1614 #define AT91_DBG_TPR 0x108 // Transmit Pointer Register
1615 #define AT91_DBG_TCR 0x10c // Transmit Counter Register
1616 #define AT91_DBG_RNPR 0x110 // Receiver Next Pointer Register
1617 #define AT91_DBG_RNCR 0x114 // Receiver Next Counter Register
1618 #define AT91_DBG_TNPR 0x118 // Transmit Next Pointer Register
1619 #define AT91_DBG_TNCR 0x11c // Transmit Next Counter Register
1620 #define AT91_DBG_PTCR 0x120 // PDC Transfer Control Register
1621 #define AT91_DBG_PTSR 0x124 // PDC Transfer Status Register
1624 //=============================================================================
1625 // Periodic Interval Timer Controller
1627 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
1630 #define AT91_PITC 0xfffffd30
1633 #define AT91_PITC_PIMR 0x00 // Period Interval Mode Register
1634 #define AT91_PITC_PIMR_PITEN (1 << 24) // Periodic Interval Timer Enable
1635 #define AT91_PITC_PIMR_PITIEN (1 << 25) // Periodic Interval Timer Intr Enable
1636 #define AT91_PITC_PISR 0x04 // Period Interval Status Register
1637 #define AT91_PITC_PISR_PITS (1 << 0) // Periodic Interval Timer Status
1638 #define AT91_PITC_PIVR 0x08 // Period Interval Status Register
1639 #define AT91_PITC_PIIR 0x0C // Period Interval Image Register
1640 #define AT91_PITC_VALUE_MASK 0x000fffff // 20-bit period value
1643 //=============================================================================
1644 // Real Time Timer Controller
1646 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
1649 #define AT91_RTTC 0xFFFFFD20
1652 #define AT91_RTTC_RTMR 0x00 // Real Time Mode Register
1653 #define AT91_RTTC_RTMR_ALMIEN (1 << 16) // Alarm Interrupt Enable
1654 #define AT91_RTTC_RTMR_RTTINCIEN (1 << 17) // Timer Increment Interrupt Enable
1655 #define AT91_RTTC_RTMR_RTTRST (1 << 18) // Timer Reset
1656 #define AT91_RTTC_RTAR 0x04 // Real Time Alarm Register
1657 #define AT91_RTTC_RTVR 0x08 // Real Time Value Register
1658 #define AT91_RTTC_RTSR 0x0C // Real Time Status Register
1659 #define AT91_RTTC_RTSR_ALMS (1 << 0) // Alarm Status
1660 #define AT91_RTTC_RTSR_RTTINC (1 << 1) // Timer Increment
1663 //=============================================================================
1666 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
1669 #define AT91_UDP 0xFFFB0000
1672 #define AT91_UDP_FRM_NUM 0x00 // Frame Number
1673 #define AT91_UDP_FRM_ERR (1 << 16) // Frame Error
1674 #define AT91_UDP_FRM_OK (1 << 17) // Frame OK
1675 #define AT91_UDP_GLB_STATE 0x04 // Global State
1676 #define AT91_UDP_GLB_FADDEN (1 << 0) // Function Address Enable
1677 #define AT91_UDP_GLB_CONFG (1 << 1) // Configured
1678 #define AT91_UDP_GLB_ESR (1 << 2) // Enable Send Resume
1679 #define AT91_UDP_GLB_RSMINPR (1 << 3) // A Resume has been seen
1680 #define AT91_UDP_GLB_RMWUPE (1 << 4) // Remote Wake Up Enable
1681 #define AT91_UDP_FADDR 0x08 // Function Address
1682 #define AT91_UDP_FADDR_FEN (1 << 8) // Function Enable
1683 #define AT91_UDP_IER 0x10 // Interrupt Enable
1684 #define AT91_UDP_EPINT0 (1 << 0) // Endpoint 0 Interrupt
1685 #define AT91_UDP_EPINT1 (1 << 1) // Endpoint 1 Interrupt
1686 #define AT91_UDP_EPINT2 (1 << 2) // Endpoint 2 Interrupt
1687 #define AT91_UDP_EPINT3 (1 << 3) // Endpoint 3 Interrupt
1688 #define AT91_UDP_EPINT4 (1 << 4) // Endpoint 4 Interrupt
1689 #define AT91_UDP_EPINT5 (1 << 5) // Endpoint 5 Interrupt
1690 #define AT91_UDP_EPINT6 (1 << 6) // Endpoint 6 Interrupt
1691 #define AT91_UDP_EPINT7 (1 << 7) // Endpoint 7 Interrupt
1692 #define AT91_UDP_RXSUSP (1 << 8) // USB Suspend Interrupt
1693 #define AT91_UDP_RXRSM (1 << 9) // USB Resume Interrupt
1694 #define AT91_UDP_EXTRSM (1 << 10) // USB External Resume Interrupt
1695 #define AT91_UDP_SOFINT (1 << 11) // USB start of frame Interrupt
1696 #define AT91_UDP_ENDBUSRES (1 << 12) // USB End of Bus Reset Interrupt
1697 #define AT91_UDP_WAKEUP (1 << 13) // USB Resume Interrupt
1698 #define AT91_UDP_IDR 0x14 // Interrupt Disable
1699 #define AT91_UDP_IMR 0x18 // Interrupt Mask
1700 #define AT91_UDP_ISR 0x1C // Interrupt Status
1701 #define AT91_UDP_ICR 0x20 // Interrupt Clear
1702 #define AT91_UDP_RST_EP 0x28 // Reset Endpoint
1703 #define AT91_UDP_CSR 0x30 // Endpoint Control and Status
1704 #define AT91_UDP_CSR_TXCOMP (1 << 0) // Generates an IN packet
1705 #define AT91_UDP_CSR_RX_DATA_BK0 (1 << 1) // Receive Data Bank 0
1706 #define AT91_UDP_CSR_RXSETUP (1 << 2) // Sends a STALL to the host
1707 #define AT91_UDP_CSR_ISOERROR (1 << 3) // Isochronous error
1708 #define AT91_UDP_CSR_TXPKTRDY (1 << 4) // Transmit Packet Ready
1709 #define AT91_UDP_CSR_FORCESTALL (1 << 5) // Force Stall
1710 #define AT91_UDP_CSR_RX_DATA_BK1 (1 << 6) // Receive Data Bank 1
1711 #define AT91_UDP_CSR_DIR (1 << 7) // Transfer Direction
1712 #define AT91_UDP_CSR_DIR_OUT (0 << 7) // Transfer Direction OUT
1713 #define AT91_UDP_CSR_DIR_IN (1 << 7) // Transfer Direction IN
1714 #define AT91_UDP_CSR_EPTYPE_CTRL (0 << 8) // Control
1715 #define AT91_UDP_CSR_EPTYPE_ISO_OUT (1 << 8) // Isochronous OUT
1716 #define AT91_UDP_CSR_EPTYPE_BULK_OUT (2 << 8) // Bulk OUT
1717 #define AT91_UDP_CSR_EPTYPE_INT_OUT (3 << 8) // Interrupt OUT
1718 #define AT91_UDP_CSR_EPTYPE_ISO_IN (5 << 8) // Isochronous IN
1719 #define AT91_UDP_CSR_EPTYPE_BULK_IN (6 << 8) // Bulk IN
1720 #define AT91_UDP_CSR_EPTYPE_INT_IN (7 << 8) // Interrupt IN
1721 #define AT91_UDP_CSR_DTGLE (1 << 11) // Data Toggle
1722 #define AT91_UDP_CSR_EPEDS (1 << 15) // Endpoint Enable Disable
1723 #define AT91_UDP_FDR 0x50 // Endpoint FIFO Data
1724 #define AT91_UDP_TXVC 0x74 // Transceiver Control
1725 #define AT91_UDP_TXVC_TXVDIS (1 << 8) // Disable Transceiver
1726 #define AT91_UDP_TXVC_PUON (1 << 9) // Pull-up ON
1729 //=============================================================================
1730 // Synchronous Serial Controller (SSC)
1732 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
1735 #define AT91_SSC 0xFFFD4000
1738 #define AT91_SSC_CR (0x00)
1739 #define AT91_SSC_CR_RXEN (1<<0) //Enable Receiver
1740 #define AT91_SSC_CR_RXDIS (1<<1) //Disable Receiver
1741 #define AT91_SSC_CR_TXEN (1<<8) //Enable Transmitter
1742 #define AT91_SSC_CR_TXDIS (1<<9) //Disable Transmitter
1743 #define AT91_SSC_CR_SWRST (1<<15) //Soft Reset
1744 #define AT91_SSC_CMR (0x04)
1745 #define AT91_SSC_RCMR (0x10)
1746 #define AT91_SSC_RCMR_CKS_DIV (0<<0) //Select Divider Clock
1747 #define AT91_SSC_RCMR_CKS_TX (1<<0) //Select Transmit Clock
1748 #define AT91_SSC_RCMR_CKS_RK (2<<0) //Select Receiver Clock
1749 #define AT91_SSC_RCMR_CKO_NONE (0<<2) //No Clock Output
1750 #define AT91_SSC_RCMR_CKO_CONT (1<<2) //Continuous Clock Output
1751 #define AT91_SSC_RCMR_CKO_TFER (2<<2) //Clock Output During Transfer only
1752 #define AT91_SSC_RCMR_CKI (1<<5) //Clock Invert
1753 #define AT91_SSC_RCMR_CKG_NONE (0<<6) //No Clock Gating, Continuous Clock
1754 #define AT91_SSC_RCMR_CKG_RFLOW (1<<6) //Clock Enabled by RF Low
1755 #define AT91_SSC_RCMR_CKG_RFHIGH (2<<6) //Clock Enabled by RF HIGH
1756 #define AT91_SSC_RCMR_START_CONT (0<<8) //Start when data in RHR, Continuous
1757 #define AT91_SSC_RCMR_START_TX (1<<8) //Start when TX Start
1758 #define AT91_SSC_RCMR_START_RFLOW (2<<8) //Start when LOW level on RF
1759 #define AT91_SSC_RCMR_START_RFHIGH (3<<8) //Start when HIGH level on RF
1760 #define AT91_SSC_RCMR_START_RFFALL (4<<8) //Start when Falling Edge on RF
1761 #define AT91_SSC_RCMR_START_RFRISE (5<<8) //Start when Rising Edge on RF
1762 #define AT91_SSC_RCMR_START_RFLEVEL (6<<8) //Start when any Level Change on RF
1763 #define AT91_SSC_RCMR_START_RFEDGE (7<<8) //Start when any Edge on RF
1764 #define AT91_SSC_RCMR_START_CMP0 (8<<8) //Start when Compare 0 match
1765 #define AT91_SSC_RCMR_STOP_CMP1 (1<<12) //Stop when Compare 1 Match
1766 #define AT91_SSC_RCMR_STTDLY(x) ((x&0xFF)<<16) //Start Delay
1767 #define AT91_SSC_RCMR_PERIOD(x) ((x&0xFF)<<24) //Frame Period
1768 #define AT91_SSC_RFMR (0x14)
1769 #define AT91_SSC_RFMR_DATLEN(x) (x&0x1F) //Data word length
1770 #define AT91_SSC_RFMR_LOOP (1<<5) //Loop Mode
1771 #define AT91_SSC_RFMR_MSBF (1<<7) //MSB First
1772 #define AT91_SSC_RFMR_DATNB(x) ((x&0xf)<<8) //Data Number, # words per frame
1773 #define AT91_SSC_RFMR_FSLEN(x) ((x&0xf)<<16) //Frame sync length
1774 #define AT91_SSC_RFMR_FSOS_NONE (0<<16) //No Frame Synch Output
1775 #define AT91_SSC_RFMR_FSOS_NEGPULSE (1<<16) //Negative Pulse Frame Sync Output
1776 #define AT91_SSC_RFMR_FSOS_POSPULSE (2<<16) //Positive Pulse Frame Sync Output
1777 #define AT91_SSC_RFMR_FSOS_LOW (3<<16) //Low Level Frame Synch Output
1778 #define AT91_SSC_RFMR_FSOS_HIGH (4<<16) //High Level Frame Synch Output
1779 #define AT91_SSC_RFMR_FSOS_TOGGLE (5<<16) //Toggle Frame Synch Output
1780 #define AT91_SSC_RFMR_FSEDGE_POS (0<<24) //Intr on +ve edge of Frame Sync
1781 #define AT91_SSC_RFMR_FSEDGE_NEG (1<<24) //Intr on -ve edge of Frame Sync
1782 #define AT91_SSC_TCMR (0x18)
1783 #define AT91_SSC_TCMR_CKS_DIV (0<<0) //Select Divider Clock
1784 #define AT91_SSC_TCMR_CKS_TX (1<<0) //Select Transmit Clock
1785 #define AT91_SSC_TCMR_CKS_RK (2<<0) //Select Receiver Clock
1786 #define AT91_SSC_TCMR_CKO_NONE (0<<2) //No Clock Output
1787 #define AT91_SSC_TCMR_CKO_CONT (1<<2) //Continuous Clock Output
1788 #define AT91_SSC_TCMR_CKO_TFER (2<<2) //Clock Output During Transfer only
1789 #define AT91_SSC_TCMR_CKI (1<<5) //Clock Invert
1790 #define AT91_SSC_TCMR_CKG_NONE (0<<6) //No Clock Gating, Continuous Clock
1791 #define AT91_SSC_TCMR_CKG_RFLOW (1<<6) //Clock Enabled by RF Low
1792 #define AT91_SSC_TCMR_CKG_RFHIGH (2<<6) //Clock Enabled by RF HIGH
1793 #define AT91_SSC_TCMR_START_CONT (0<<8) //Start when data in THR, Continuous
1794 #define AT91_SSC_TCMR_START_TX (1<<8) //Start when TX Start
1795 #define AT91_SSC_TCMR_START_RFLOW (2<<8) //Start when LOW level on RF
1796 #define AT91_SSC_TCMR_START_RFHIGH (3<<8) //Start when HIGH level on RF
1797 #define AT91_SSC_TCMR_START_RFFALL (4<<8) //Start when Falling Edge on RF
1798 #define AT91_SSC_TCMR_START_RFRISE (5<<8) //Start when Rising Edge on RF
1799 #define AT91_SSC_TCMR_START_RFLEVEL (6<<8) //Start when any Level Change on RF
1800 #define AT91_SSC_TCMR_START_RFEDGE (6<<8) //Start when any Edge on RF
1801 #define AT91_SSC_TCMR_STDDLY(x) ((x&0xFF)<<16) //Start Delay
1802 #define AT91_SSC_TCMR_PERIOD(x) ((x&0xFF)<<24) //Frame Period
1803 #define AT91_SSC_TFMR (0x1C)
1804 #define AT91_SSC_TFMR_DATLEN(x) (x&0x1F) //Data word length
1805 #define AT91_SSC_TFMR_DATDEF (1<<5) //Default Data is 1's
1806 #define AT91_SSC_TFMR_MSBF (1<<7) //MSB First
1807 #define AT91_SSC_TFMR_DATNB(x) ((x&0xf)<<8) //Data Number, # words per frame
1808 #define AT91_SSC_TFMR_FSLEN(x) ((x&0xf)<<16) //Frame sync length
1809 #define AT91_SSC_TFMR_FSOS_NONE (0<<16) //No Frame Synch Output
1810 #define AT91_SSC_TFMR_FSOS_NEGPULSE (1<<16) //Negative Pulse Frame Sync Output
1811 #define AT91_SSC_TFMR_FSOS_POSPULSE (2<<16) //Positive Pulse Frame Sync Output
1812 #define AT91_SSC_TFMR_FSOS_LOW (3<<16) //Low Level Frame Synch Output
1813 #define AT91_SSC_TFMR_FSOS_HIGH (4<<16) //High Level Frame Synch Output
1814 #define AT91_SSC_TFMR_FSOS_TOGGLE (5<<16) //Toggle Frame Synch Output
1815 #define AT91_SSC_RFMR_FSDEN_DEF (0<<23) //Frame Sync is Default Data
1816 #define AT91_SSC_RFMR_FSDEN_TSHR (1<<23) //Frame Sync is TSHR Data
1817 #define AT91_SSC_RFMR_FSEDGE_POS (0<<24) //Intr on +ve edge of Frame Sync
1818 #define AT91_SSC_RFMR_FSEDGE_NEG (1<<24) //Intr on -ve edge of Frame Sync
1819 #define AT91_SSC_RHR (0x20)
1820 #define AT91_SSC_THR (0x24)
1821 #define AT91_SSC_RSHR (0x30)
1822 #define AT91_SSC_TSHR (0x34)
1823 #define AT91_SSC_RC0R (0x38)
1824 #define AT91_SSC_RC1R (0x3C)
1825 #define AT91_SSC_SR (0x40)
1826 #define AT91_SSC_SR_TXRDY (1<<0) //Transmit Ready
1827 #define AT91_SSC_SR_TXEMPTY (1<<1) //Transmit Empty
1828 #define AT91_SSC_SR_ENDTX (1<<2) //End of Transmission
1829 #define AT91_SSC_SR_TXBUFE (1<<3) //Transmit Buffer Empty
1830 #define AT91_SSC_SR_RXRDY (1<<4) //Receiver Ready
1831 #define AT91_SSC_SR_OVRUN (1<<5) //Receiver Overrun
1832 #define AT91_SSC_SR_ENDRX (1<<6) //End of Reception
1833 #define AT91_SSC_SR_RXBUFF (1<<7) //Receive Buffer Full
1834 #define AT91_SSC_SR_CP0 (1<<8) //Compare 0 match
1835 #define AT91_SSC_SR_CP1 (1<<9) //Compare 1 Match
1836 #define AT91_SSC_SR_TXSYN (1<<10) //Transmit Frame Sync
1837 #define AT91_SSC_SR_RXSYN (1<<11) //Receive Frame Sync
1838 #define AT91_SSC_SR_TXEN (1<<16) //Transmitter Enabled
1839 #define AT91_SSC_SR_RXEN (1<<17) //Receiver Enabled
1840 #define AT91_SSC_IER (0x44)
1841 #define AT91_SSC_IDR (0x48)
1842 #define AT91_SSC_IMR (0x4C)
1844 #define AT91_SSC_RPR 0x100 // Receiver Pointer Register
1845 #define AT91_SSC_RCR 0x104 // Receiver Counter Register
1846 #define AT91_SSC_TPR 0x108 // Transmit Pointer Register
1847 #define AT91_SSC_TCR 0x10c // Transmit Counter Register
1848 #define AT91_SSC_RNPR 0x110 // Receiver Next Pointer Register
1849 #define AT91_SSC_RNCR 0x114 // Receiver Next Counter Register
1850 #define AT91_SSC_TNPR 0x118 // Transmit Next Pointer Register
1851 #define AT91_SSC_TNCR 0x11c // Transmit Next Counter Register
1852 #define AT91_SSC_PTCR 0x120 // PDC Transfer Control Register
1853 #define AT91_SSC_PTSR 0x124 // PDC Transfer Status Register
1855 #define AT91_SSC_PTCR_RXTEN (1 << 0) //Receive Transfers Enabled
1856 #define AT91_SSC_PTCR_RXTDIS (1 << 1) //Receive Transfers Disabled
1857 #define AT91_SSC_PTCR_TXTEN (1 << 8) //Receive Transfers Enabled
1858 #define AT91_SSC_PTCR_TXTDIS (1 << 9) //Receive Transfers Disabled
1862 //=============================================================================
1863 // Ethernet Controller (EMAC)
1865 #if defined(CYGHWR_HAL_ARM_AT91SAM7X)
1868 #define AT91_EMAC 0xFFFBC000
1871 #define AT91_EMAC_NCR (0x00) // Network Control
1872 #define AT91_EMAC_NCR_LB (1 << 0) // Loopback
1873 #define AT91_EMAC_NCR_LBL (1 << 1) // Loopback Local
1874 #define AT91_EMAC_NCR_RE (1 << 2) // Receiver Enable
1875 #define AT91_EMAC_NCR_TX (1 << 3) // Transmit Enable
1876 #define AT91_EMAC_NCR_MPE (1 << 4) // Management Port Enable
1877 #define AT91_EMAC_NCR_CSR (1 << 5) // Clear Statistics Registers
1878 #define AT91_EMAC_NCR_ISR (1 << 6) // Increment Statistics Registers
1879 #define AT91_EMAC_NCR_WES (1 << 7) // Write Enable for Statistics Registers
1880 #define AT91_EMAC_NCR_BP (1 << 8) // Back Pressure
1881 #define AT91_EMAC_NCR_TSTART (1 << 9) // Start Transmitter
1882 #define AT91_EMAC_NCR_THALT (1 << 10) // Halt Transmitter
1884 #define AT91_EMAC_NCFG (0x04) // Network Configuration
1885 #define AT91_EMAC_NCFG_SPD_10Mbps (0 << 0) // 10Mbps line speed
1886 #define AT91_EMAC_NCFG_SPD_100Mbps (1 << 0) // 100Mbps line speed
1887 #define AT91_EMAC_NCFG_FD (1 << 1) // Full Deplex
1888 #define AT91_EMAC_NCFG_BR (1 << 2) // Bit Rate
1889 #define AT91_EMAC_NCFG_CAF (1 << 4) // Copy All Frames
1890 #define AT91_EMAC_NCFG_NBC (1 << 5) // Don't receiver Broadcasts
1891 #define AT91_EMAC_NCFG_MTI (1 << 6) // Multicast Hash Enable
1892 #define AT91_EMAC_NCFG_UNI (1 << 7) // Unicast hash enable
1893 #define AT91_EMAC_NCFG_BIG (1 << 8) // Receive upto 1522 byte frames
1894 #define AT91_EMAC_NCFG_EAE (1 << 9) // External Address match Enable
1895 #define AT91_EMAC_NCFG_CLK_HCLK_8 (0 << 10) // HCLK divided by 8
1896 #define AT91_EMAC_NCFG_CLK_HCLK_16 (1 << 10) // HCLK divided by 16
1897 #define AT91_EMAC_NCFG_CLK_HCLK_32 (2 << 10) // HCLK divided by 32
1898 #define AT91_EMAC_NCFG_CLK_HCLK_64 (3 << 10) // HCLK divided by 64
1899 #define AT91_EMAC_NCFG_CLK_MASK (3 << 10) // HCLK mask
1900 #define AT91_EMAC_NCFG_CLK_RTY (1 << 12) // Retry Test
1901 #define AT91_EMAC_NCFG_CLK_RMII (1 << 13) // Enable RMII mode
1902 #define AT91_EMAC_NCFG_CLK_MII (0 << 13) // Enable MII mode
1903 #define AT91_EMAC_NCFG_RLCE (0 << 16) // Receive Length Check Enable
1905 #define AT91_EMAC_NSR (0x08) // Network Status
1906 #define AT91_EMAC_NSR_MDIO_MASK (1 << 1) // MDIO Pin status
1907 #define AT91_EMAC_NSR_IDLE (1 << 2) // PHY logical is idle
1909 #define AT91_EMAC_TSR (0x14) // Transmit Status
1910 #define AT91_EMAC_TSR_OVR (1 << 0) // Overrun
1911 #define AT91_EMAC_TSR_COL (1 << 1) // Collision occurred
1912 #define AT91_EMAC_TSR_RLE (1 << 2) // Retry Limit Exceeded
1913 #define AT91_EMAC_TSR_TXIDLE (1 << 3) // Transmitter Idle
1914 #define AT91_EMAC_TSR_BNQ (1 << 4) // Buffer Not Queues
1915 #define AT91_EMAC_TSR_COMP (1 << 5) // Transmission Complete
1916 #define AT91_EMAC_TSR_UND (1 << 6) // Transmit Underrun
1918 #define AT91_EMAC_RBQP (0x18) // Receiver Buffer Queue Pointer
1919 #define AT91_EMAC_TBQP (0x1c) // Transmit Buffer Queue Pointer
1921 #define AT91_EMAC_RSR (0x20) // Receiver Status
1922 #define AT91_EMAC_RSR_BNA (1 << 0) // Buffer Not Available
1923 #define AT91_EMAC_RSR_REC (1 << 1) // Frame Received
1924 #define AT91_EMAC_RSR_OVR (1 << 2) // Transmit Buffer Overrun
1926 #define AT91_EMAC_ISR (0x24) // Interrupt Status
1927 #define AT91_EMAC_ISR_DONE (1 << 0) // Management Done
1928 #define AT91_EMAC_ISR_RCOM (1 << 1) // Receiver Complete
1929 #define AT91_EMAC_ISR_RBNA (1 << 2) // Receiver Buffer Not Available
1930 #define AT91_EMAC_ISR_TOVR (1 << 3) // Transmit Buffer Overrun
1931 #define AT91_EMAC_ISR_TUND (1 << 4) // Transmit Error: Buffer under run
1932 #define AT91_EMAC_ISR_RTRY (1 << 5) // Transmit Error: Retry Limit Exceeded
1933 #define AT91_EMAC_ISR_TBRE (1 << 6) // Transmit Buffer Register Empty
1934 #define AT91_EMAC_ISR_TCOM (1 << 7) // Transmit Complete
1935 #define AT91_EMAC_ISR_TIDLE (1 << 8) // Transmitter Idle
1936 #define AT91_EMAC_ISR_LINK (1 << 9) // Link pin changed state
1937 #define AT91_EMAC_ISR_ROVR (1 << 10) // Receiver Overrun
1938 #define AT91_EMAC_ISR_HRESP (1 << 11) // HRESP not OK
1939 #define AT91_EMAC_IER (0x28) // Interrupt Enable
1940 #define AT91_EMAC_IDR (0x2c) // Interrupt Disable
1941 #define AT91_EMAC_IMR (0x30) // Interrupt Mask
1943 #define AT91_EMAC_MAN (0x34) // PHY Maintenance
1944 #define AT91_EMAC_MAN_DATA_MASK (0xffff<<0) // Data to/from PHY
1945 #define AT91_EMAC_MAN_CODE (2<<16) // Code
1946 #define AT91_EMAC_MAN_REGA_MASK (0x1f<<18) // Register Address Mask
1947 #define AT91_EMAC_MAN_REGA_SHIFT (18) // Register Address Shift
1948 #define AT91_EMAC_MAN_PHY_MASK (0x1f<<23) // PHY Address Mask
1949 #define AT91_EMAC_MAN_PHY_SHIFT (23) // PHY Address Shift
1950 #define AT91_EMAC_MAN_RD (2<<28) // Read operation
1951 #define AT91_EMAC_MAN_WR (1<<28) // Write Operation
1952 #define AT91_EMAC_MAN_SOF (1<<30) // Must be set to 01
1953 #define AT91_EMAC_MAN_PHYA(x) ((x&0x1f)<<23) // Create a PHY Address
1954 #define AT91_EMAC_MAN_REGA(x) ((x&0x1f)<<18) // Create a Register Address
1955 #define AT91_EMAC_MAN_DATA(x) (x&0xffff) // Create a Data word
1958 #define AT91_EMAC_PTR (0x38) // Pause Time Register
1959 #define AT91_EMAC_PFR (0x3C) // Pause Frames Received
1960 #define AT91_EMAC_FTO (0x40) // Frames Transmitted OK
1961 #define AT91_EMAC_SCF (0x44) // Single Collision Frame
1962 #define AT91_EMAC_MCF (0x48) // Multiple Collision Frame
1963 #define AT91_EMAC_FRO (0x4c) // Frames Received OK
1964 #define AT91_EMAC_FCSE (0x50) // Frame Check Sequence Error
1965 #define AT91_EMAC_ALE (0x54) // Alignment Error
1966 #define AT91_EMAC_DTR (0x58) // Deferred Transmission Frame
1967 #define AT91_EMAC_LCOL (0x5c) // Late Collision
1968 #define AT91_EMAC_XCOL (0x60) // Excessive Collisions - ECOL!!
1969 #define AT91_EMAC_TUND (0x64) // Transmit Underrun Error
1970 #define AT91_EMAC_CSE (0x68) // Carrier Sense Error
1971 #define AT91_EMAC_RRE (0x6c) // Receive Resource Errors
1972 #define AT91_EMAC_ROV (0x70) // Receive Overrun
1973 #define AT91_EMAC_RSE (0x74) // Receiver Symbol erros
1974 #define AT91_EMAC_ELE (0x78) // Excessive Length Errors
1975 #define AT91_EMAC_RJE (0x7c) // Receive Jabber Errors
1976 #define AT91_EMAC_USF (0x80) // Undersize Frame Errors
1977 #define AT91_EMAC_STE (0x84) // SQE Test Errors
1978 #define AT91_EMAC_RLE (0x88) // Receive Length Field Mismatch
1980 #define AT91_EMAC_HRB (0x90) // Hash Address Low [31:0]
1981 #define AT91_EMAC_HRT (0x94) // Hash Address High [63:32]
1982 #define AT91_EMAC_SA1L (0x98) // Specific Address 1 Low, First 4 bytes
1983 #define AT91_EMAC_SA1H (0x9c) // Specific Address 1 High, Last 2 bytes
1984 #define AT91_EMAC_SA2L (0xa0) // Specific Address 2 Low, First 4 bytes
1985 #define AT91_EMAC_SA2H (0xa4) // Specific Address 2 High, Last 2 bytes
1986 #define AT91_EMAC_SA3L (0xa8) // Specific Address 3 Low, First 4 bytes
1987 #define AT91_EMAC_SA3H (0xac) // Specific Address 3 High, Last 2 bytes
1988 #define AT91_EMAC_SA4L (0xb0) // Specific Address 4 Low, First 4 bytes
1989 #define AT91_EMAC_SA4H (0xb4) // Specific Address 4 High, Last 2 bytes
1990 #define AT91_EMAC_TID (0xb8) // Type ID Checking Register
1992 #define AT91_EMAC_USRIO (0xc0) // User IO Register
1993 #define AT91_EMAC_USRIO_RMII (1<<0) // RMII Mode
1994 #define AT91_EMAC_USRIO_CLKEN (1<<1) // Clock Enable
1996 // Receiver Buffer Descriptor
1997 #define AT91_EMAC_RBD_ADDR 0x0 // Address to beginning of buffer
1998 #define AT91_EMAC_RBD_ADDR_MASK (0xFFFFFFFC) // Address Mask masking the reserved bits
1999 #define AT91_EMAC_RBD_ADDR_OWNER_EMAC (0 << 0) // EMAC owns receiver buffer
2000 #define AT91_EMAC_RBD_ADDR_OWNER_SW (1 << 0) // SW owns receiver buffer
2001 #define AT91_EMAC_RBD_ADDR_WRAP (1 << 1) // Last receiver buffer
2002 #define AT91_EMAC_RBD_SR 0x1 // Buffer Status
2003 #define AT91_EMAC_RBD_SR_LEN_MASK (0xfff) // Length of data
2004 #define AT91_EMAC_RBD_SR_SOF (1 << 14) // Start of Frame
2005 #define AT91_EMAC_RBD_SR_EOF (1 << 15) // End of Frame
2006 #define AT91_EMAC_RBD_SR_CFI (1 << 16) // Concatination Format Ind
2007 #define AT91_EMAC_RDB_SR_VLAN_SHIFT (17) // VLAN priority tag
2008 #define AT91_EMAC_RDB_SR_VLAN_MASK (7 << 17)
2009 #define AT91_EMAC_RDB_SR_PRIORTY_TAG (1 << 20) // Priority Tag Detected
2010 #define AT91_EMAC_RDB_SR_VLAN_TAG (1 << 21) // Priority Tag Detected
2011 #define AT91_EMAC_RBD_SR_TYPE_ID (1 << 22) // Type ID match
2012 #define AT91_EMAC_RBD_SR_SA4M (1 << 23) // Specific Address 4 match
2013 #define AT91_EMAC_RBD_SR_SA3M (1 << 24) // Specific Address 3 match
2014 #define AT91_EMAC_RBD_SR_SA2M (1 << 25) // Specific Address 2 match
2015 #define AT91_EMAC_RBD_SR_SA1M (1 << 26) // Specific Address 1 match
2016 #define AT91_EMAC_RBD_SR_EXTNM (1 << 28) // External Address match
2017 #define AT91_EMAC_RBD_SR_UNICAST (1 << 29) // Unicast hash match
2018 #define AT91_EMAC_RBD_SR_MULTICAST (1 << 30) // Multicast hash match
2019 #define AT91_EMAC_RBD_SR_BROADCAST (1 << 31) // Broadcast
2021 // Transmit Buffer Descriptor
2022 #define AT91_EMAC_TBD_ADDR 0x0 // Address to beginning of buffer
2023 #define AT91_EMAC_TBD_SR 0x1 // Buffer Status
2024 #define AT91_EMAC_TBD_SR_LEN_MASK (0xfff) // Length of data
2025 #define AT91_EMAC_TBD_SR_EOF (1 << 15) // End of Frame
2026 #define AT91_EMAC_TBD_SR_NCRC (1 << 16) // No CRC added by EMAC
2027 #define AT91_EMAC_TBD_SR_EXHAUST (1 << 27) // Buffers exhausted
2028 #define AT91_EMAC_TBD_SR_TXUNDER (1 << 28) // Transmit Underrun
2029 #define AT91_EMAC_TBD_SR_RTRY (1 << 29) // Retry limit exceeded
2030 #define AT91_EMAC_TBD_SR_WRAP (1 << 30) // Marks last descriptor
2031 #define AT91_EMAC_TBD_SR_USED (1 << 31) // Buffer used
2035 //=============================================================================
2036 // Two Wire Interface (TWI)
2038 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
2041 #define AT91_TWI 0xFFFB8000
2044 #define AT91_TWI_CR 0x00 // Control
2045 #define AT91_TWI_CR_START (1 << 0) // Send a Start
2046 #define AT91_TWI_CR_STOP (1 << 1) // Send a Stop
2047 #define AT91_TWI_CR_MSEN (1 << 2) // Master Transfer Enable
2048 #define AT91_TWI_CR_MSDIS (1 << 3) // Master Transfer Disable
2049 #define AT91_TWI_CR_SVEN (1 << 4) // Slave Transfer Enable
2050 #define AT91_TWI_CR_SDIS (1 << 5) // Slave Transfer Disable
2051 #define AT91_TWI_CR_SWRST (1 << 7) // Software Reset
2052 #define AT91_TWI_MMR 0x04 // Master Mode
2053 #define AT91_TWI_MMR_IADRZ_NO (0 << 8) // Internal Device Address size 0Bytes
2054 #define AT91_TWI_MMR_IADRZ_1 (1 << 8) // Internal Device Address size 1Byte
2055 #define AT91_TWI_MMR_IADRZ_2 (2 << 8) // Internal Device Address size 2Bytes
2056 #define AT91_TWI_MMR_IADRZ_3 (3 << 8) // Internal Device Address size 3Bytes
2057 #define AT91_TWI_MMR_MWRITE (0 << 12) // Master Write
2058 #define AT91_TWI_MMR_MREAD (1 << 12) // Master Read
2059 #define AT91_TWI_MMR_DADR_MASK (0x3f << 16) // Device Address Mask
2060 #define AT91_TWI_MMR_DADR_SHIFT (16) // Device Address Shift
2061 #define AT91_TWI_SMR 0x08 // Slave Mode
2062 #define AT91_TWI_SMR_SADR_MASK (0x3f << 16) // Slave Device Address Mask
2063 #define AT91_TWI_SMR_SADR_SHIFT (16) // Slave Device Address Shift
2064 #define AT91_TWI_IADR 0x0C // Internal Address
2065 #define AT91_TWI_CWGR 0x10 // Clock Waveform Generator
2066 #define AT91_TWI_CWGR_CLDIV_MASK (0xf << 0) // Clock Low Divider Mask
2067 #define AT91_TWI_CWGR_CLDIV_SHIFT (00) // Clock Low Divider Shift
2068 #define AT91_TWI_CWGR_CHDIV_MASK (0xf << 8) // Clock High Divider Mask
2069 #define AT91_TWI_CWGR_CHDIV_SHIFT (08) // Clock High Divider Shift
2070 #define AT91_TWI_CWGR_CKDIV_MASK (0x7 << 16) // Clock Divider Mask
2071 #define AT91_TWI_CWGR_CKDIV_SHIFT (16) // Clock Divider Shift
2072 #define AT91_TWI_SR 0x20 // Status
2073 #define AT91_TWI_SR_TXCOMP (1 << 0) // Transmission Completed
2074 #define AT91_TWI_SR_RXRDY (1 << 1) // Receiver Holding Register Ready
2075 #define AT91_TWI_SR_TXRDY (1 << 2) // Transmit Holding Register Ready
2076 #define AT91_TWI_SR_SVREAD (1 << 3) // Slave Read
2077 #define AT91_TWI_SR_SVACC (1 << 4) // Slave Access
2078 #define AT91_TWI_SR_GCACC (1 << 5) // General Call Access
2079 #define AT91_TWI_SR_OVRE (1 << 6) // Overrun Error
2080 #define AT91_TWI_SR_UNRE (1 << 7) // Underrun Error
2081 #define AT91_TWI_SR_NACK (1 << 8) // Not Acknowledged
2082 #define AT91_TWI_SR_ARBLST (1 << 9) // Arbitration Lost
2083 #define AT91_TWI_IER 0x24 // Interrupt Enable
2084 #define AT91_TWI_IDR 0x28 // Interrupt Disable
2085 #define AT91_TWI_IMR 0x2C // Interrupt Mask
2086 #define AT91_TWI_RHR 0x30 // Receiver Holding
2087 #define AT91_TWI_THR 0x34 // Transmit Holding
2090 //=============================================================================
2091 // Analog to Digital Convertor (ADC)
2093 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
2096 #define AT91_ADC 0xFFFD8000
2099 #define AT91_ADC_CR 0x00 // Control
2100 #define AT91_ADC_CR_SWRST (1 << 0) // Software Reset
2101 #define AT91_ADC_CR_START (1 << 1) // Start Conversion
2102 #define AT91_ADC_MR 0x04 // Mode
2103 #define AT91_ADC_MR_TRGSEL_TIOA0 (0 << 1) // Trigger = TIAO0
2104 #define AT91_ADC_MR_TRGSEL_TIOA1 (1 << 1) // Trigger = TIAO1
2105 #define AT91_ADC_MR_TRGSEL_TIOA2 (2 << 1) // Trigger = TIAO2
2106 #define AT91_ADC_MR_TRGSEL_TIOA3 (3 << 1) // Trigger = TIAO3
2107 #define AT91_ADC_MR_TRGSEL_TIOA4 (4 << 1) // Trigger = TIAO4
2108 #define AT91_ADC_MR_TRGSEL_TIOA5 (5 << 1) // Trigger = TIAO5
2109 #define AT91_ADC_MR_TRGSEL_EXT (6 << 1) // Trigger = External
2110 #define AT91_ADC_MR_LOWREC_10BITS (0 << 4) // 10-bit Resolution
2111 #define AT91_ADC_MR_LOWRES_8BITS (1 << 4) // 8-bit resolution
2112 #define AT91_ADC_MR_SLEEP_ON (1 << 5) // Sleep mode on
2113 #define AT91_ADC_MR_SLEEP_OFF (0 << 5) // Sleep mode off
2114 #define AT91_ADC_MR_PRESCAL_MASK (0x3f << 8) // Prescale Mask
2115 #define AT91_ADC_MR_PRESCAL_SHIFT (8) // Prescale Shift
2116 #define AT91_ADC_MR_STARTUP_MASK (0x0f << 16) // Startup Time Mask
2117 #define AT91_ADC_MR_STARTUP_SHIFT (16) // Startup Time Mask
2118 #define AT91_ADC_MR_SHTIM_MASK (0x0f << 24) // Sample & Hold Time Mask
2119 #define AT91_ADC_MR_SHTIM_SHIFT (24) // Sample & Hold Time Shift
2120 #define AT91_ADC_CHER 0x10 // Channel Enable
2121 #define AT91_ADC_CHER_CH0 (1 << 0) // Channel 0
2122 #define AT91_ADC_CHER_CH1 (1 << 1) // Channel 1
2123 #define AT91_ADC_CHER_CH2 (1 << 2) // Channel 2
2124 #define AT91_ADC_CHER_CH3 (1 << 3) // Channel 3
2125 #define AT91_ADC_CHER_CH4 (1 << 4) // Channel 4
2126 #define AT91_ADC_CHER_CH5 (1 << 5) // Channel 5
2127 #define AT91_ADC_CHER_CH6 (1 << 6) // Channel 6
2128 #define AT91_ADC_CHER_CH7 (1 << 7) // Channel 7
2129 #define AT91_ADC_CHDR 0x14 // Channel Disable
2130 #define AT91_ADC_CHSR 0x18 // Channel Status
2131 #define AT91_ADC_SR 0x1c // Status
2132 #define AT91_ADC_CHSR_EOC0 (1 << 0) // Channel 0 End of Conversion
2133 #define AT91_ADC_CHSR_EOC1 (1 << 1) // Channel 1 End of Conversion
2134 #define AT91_ADC_CHSR_EOC2 (1 << 2) // Channel 2 End of Conversion
2135 #define AT91_ADC_CHSR_EOC3 (1 << 3) // Channel 3 End of Conversion
2136 #define AT91_ADC_CHSR_EOC4 (1 << 4) // Channel 4 End of Conversion
2137 #define AT91_ADC_CHSR_EOC5 (1 << 5) // Channel 5 End of Conversion
2138 #define AT91_ADC_CHSR_EOC6 (1 << 6) // Channel 6 End of Conversion
2139 #define AT91_ADC_CHSR_EOC7 (1 << 7) // Channel 7 End of Conversion
2140 #define AT91_ADC_CHSR_OVRE0 (1 << 8) // Channel 0 Overrun Error
2141 #define AT91_ADC_CHSR_OVRE1 (1 << 9) // Channel 1 Overrun Error
2142 #define AT91_ADC_CHSR_OVRE2 (1 << 10) // Channel 2 Overrun Error
2143 #define AT91_ADC_CHSR_OVRE3 (1 << 11) // Channel 3 Overrun Error
2144 #define AT91_ADC_CHSR_OVRE4 (1 << 12) // Channel 4 Overrun Error
2145 #define AT91_ADC_CHSR_OVRE5 (1 << 13) // Channel 5 Overrun Error
2146 #define AT91_ADC_CHSR_OVRE6 (1 << 14) // Channel 6 Overrun Error
2147 #define AT91_ADC_CHSR_OVRE7 (1 << 15) // Channel 7 Overrun Error
2148 #define AT91_ADC_CHSR_DRDY (1 << 16) // Data Ready
2149 #define AT91_ADC_CHSR_GOVER (1 << 17) // General Overrun
2150 #define AT91_ADC_CHSR_EDNRX (1 << 18) // End of Receiver Transfer
2151 #define AT91_ADC_CHSR_RXBUFF (1 << 19) // RXBUFFER Interrupt
2152 #define AT91_ADC_LCDR 0x20 // Last Converted Data
2153 #define AT91_ADC_IER 0x24 // Interrupt Enable
2154 #define AT91_ADC_IDR 0x28 // Interrupt Disable
2155 #define AT91_ADC_IMR 0x2c // Interrupt Mask
2156 #define AT91_ADC_CDR0 0x30 // Channel Data 0
2157 #define AT91_ADC_CDR1 0x34 // Channel Data 1
2158 #define AT91_ADC_CDR2 0x38 // Channel Data 2
2159 #define AT91_ADC_CDR3 0x3c // Channel Data 3
2160 #define AT91_ADC_CDR4 0x40 // Channel Data 4
2161 #define AT91_ADC_CDR5 0x44 // Channel Data 5
2162 #define AT91_ADC_CDR6 0x48 // Channel Data 6
2163 #define AT91_ADC_CDR7 0x4c // Channel Data 7
2164 #define AT91_ADC_RPR 0x100 // Receive Pointer
2165 #define AT91_ADC_RCR 0x104 // Receive Counter
2166 #define AT91_ADC_TPR 0x108 // Transmit Pointer
2167 #define AT91_ADC_TCR 0x10C // Transmit Counter
2168 #define AT91_ADC_RNPR 0x110 // Receive Next Pointer
2169 #define AT91_ADC_RNCR 0x114 // Receive Next Counter
2170 #define AT91_ADC_TNPR 0x118 // Transmit Next Pointer
2171 #define AT91_ADC_TNCR 0x11C // Transmit Next Counter
2172 #define AT91_ADC_PTCR 0x120 // PDC Transfer Control
2173 #define AT91_ADC_PTSR 0x124 // PDC Transfer Status
2177 //=============================================================================
2178 // Controller Area Network (CAN)
2180 #if defined(CYGHWR_HAL_ARM_AT91SAM7X)
2183 #define AT91_CAN 0xFFFD8000
2186 #define AT91_CAN_MR 0x000 // Mode
2187 #define AT91_CAN_MR_CANEN (1 << 0) // Enable
2188 #define AT91_CAN_MR_LPM (1 << 1) // Enable Low Power Mode
2189 #define AT91_CAN_MR_ABM (1 << 2) // Enable Autobaud/Listen mode
2190 #define AT91_CAN_MR_OVL (1 << 3) // Enable Overload Frame
2191 #define AT91_CAN_MR_TEOF (1 << 4) // Timestamp at End Of Trame
2192 #define AT91_CAN_MR_TTM (1 << 5) // Enable Time Triggered Mode
2193 #define AT91_CAN_MR_TIMFRZ (1 << 6) // Enable Timer Freeze
2194 #define AT91_CAN_MR_DRPT (1 << 7) // Disable Repeat
2195 #define AT91_CAN_IER 0x004 // Interrupt Enable
2196 #define AT91_CAM_IER_MB0 (1 << 0) // Mailbox 0
2197 #define AT91_CAM_IER_MB1 (1 << 1) // Mailbox 1
2198 #define AT91_CAM_IER_MB2 (1 << 2) // Mailbox 2
2199 #define AT91_CAM_IER_MB3 (1 << 3) // Mailbox 3
2200 #define AT91_CAM_IER_MB4 (1 << 4) // Mailbox 4
2201 #define AT91_CAM_IER_MB5 (1 << 5) // Mailbox 5
2202 #define AT91_CAM_IER_MB6 (1 << 6) // Mailbox 6
2203 #define AT91_CAM_IER_MB7 (1 << 7) // Mailbox 7
2204 #define AT91_CAM_IER_ERRA (1 << 16) // Error Active Mode
2205 #define AT91_CAM_IER_WARN (1 << 17) // Warning Limit
2206 #define AT91_CAM_IER_ERRO (1 << 18) // Error Passive Mode
2207 #define AT91_CAM_IER_BOFF (1 << 19) // Bus-Off Mode
2208 #define AT91_CAM_IER_SLEEP (1 << 20) // Sleep
2209 #define AT91_CAM_IER_WAKEUP (1 << 21) // Wakeup
2210 #define AT91_CAM_IER_TOVF (1 << 22) // Timer Overflow
2211 #define AT91_CAM_IER_TSTP (1 << 23) // TimeStamp
2212 #define AT91_CAM_IER_CERR (1 << 24) // CRC Error
2213 #define AT91_CAM_IER_SERR (1 << 25) // Stuffing Error
2214 #define AT91_CAM_IER_AERR (1 << 26) // Acknowledgement Error
2215 #define AT91_CAM_IER_FERR (1 << 27) // Form Error
2216 #define AT91_CAM_IER_BERR (1 << 28) // Bit Error
2217 #define AT91_CAN_IDR 0x008 // Interrupt Disable
2218 #define AT91_CAN_IMR 0x00C // Interrupt Mask
2219 #define AT91_CAN_SR 0x010 // Status
2220 #define AT91_CAN_SR_RBSY (1 << 29) // Receiver busy
2221 #define AT91_CAM_SR_TBSY (1 << 30) // Transmitter busy
2222 #define AT91_CAM_IER_OVLSY (1 << 31) // Overload Busy
2223 #define AT91_CAN_BR 0x014 // Baudrate
2224 #define AT91_CAN_BR_PHASE1_MASK (0x7 << 4) // Phase 1 Segment mask
2225 #define AT91_CAN_BR_PHASE1_SHIFT (4) // Phase 1 Segment shift
2226 #define AT91_CAN_BR_PHASE2_MASK (0x7 << 0) // Phase 2 Segment mask
2227 #define AT91_CAN_BR_PHASE2_SHIFT (0) // Phase 2 Segment shift
2228 #define AT91_CAN_BR_PROPAG_MASK (0x7 << 8) // Programming Time Segment mask
2229 #define AT91_CAN_BR_PROPAG_SHIFT (8) // Programming Time Segment shift
2230 #define AT91_CAN_BR_SJW_MASK (0x3 << 12) // Re-Sync jump width mask
2231 #define AT91_CAN_BR_SJW_SHIFT (12) // Re-Sync jump width shift
2232 #define AT91_CAN_BR_BRP_MASK (0x7f << 16) // Baudrate Prescaler mask
2233 #define AT91_CAN_BR_BRP_SHIFT (16) // Baudrate Prescaler mask
2234 #define AT91_CAN_BR_SMP_ONCE (0 << 24) // Sampling once
2235 #define AT91_CAN_BR_SMP_THRICE (1 << 24) // Sampling three times
2236 #define AT91_CAN_TIM 0x018 // Timer
2237 #define AT91_CAN_TIMESTP 0x01c // Timestamp
2238 #define AT91_CAN_ECR 0x020 // Error Counter
2239 #define AT91_CAN_ECR_REC_MASK (0xf << 0) // Receiver Error Counter mask
2240 #define AT91_CAN_ECR_REC_SHIFT (00) // Receiver Error Counter shift
2241 #define AT91_CAN_ECR_TEC_MASK (0xf << 16) // Transmit Error Counter mask
2242 #define AT91_CAN_ECR_TEC_SHIFT (00) // Transmit Error Counter shift
2243 #define AT91_CAN_TCR 0x024 // Transfer Command
2244 #define AT91_CAN_TCR_TIMRST (1 << 31) // Timer Reset
2245 #define AT91_CAN_ACR 0x028 // Abort Command
2246 #define AT91_CAN_MMR0 0x200 // Mailbox 0 Mode
2247 #define AT91_CAN_MMR_PRIOR_MASK (0xf << 16) // Priority Mask
2248 #define AT91_CAN_MMR_PRIOR_SHIFT (16) // Priority Shift
2249 #define AT91_CAN_MMR_MOT_DISABLED (0 << 24) // Mailbox disabled
2250 #define AT91_CAN_MMR_MOT_RECEPTION (1 << 24) // Reception Mailbox
2251 #define AT91_CAN_MMR_MOT_RECEPTION_OVER (2 << 24) // Reception with Overwrite
2252 #define AT91_CAM_MMR_MOT_TRANSMIT (3 << 24) // Transmit Mailbox
2253 #define AT91_CAM_MMR_MOT_CONSUMER (4 << 24) // Transmit Mailbox
2254 #define AT91_CAM_MMR_MOT_PRODUCER (5 << 24) // Transmit Mailbox
2255 #define AT91_CAN_MAM0 0x204 // Mailbox 0 Acceptance Mask
2256 #define AT91_CAM_MAM_MIDvB_MASK (0x3ffff << 0) // MIDvB mask
2257 #define AT91_CAM_MAM_MIDvB_SHIFT (0) // MIDvB shift
2258 #define AT91_CAM_MAM_MIDvA_MASK (0x7ff << 18) // MIDvB mask
2259 #define AT91_CAM_MAM_MIDvA_SHIFT (18) // MIDvB shift
2260 #define AT91_CAM_MAM_MIDE (1 << 29) // Identifier Version
2261 #define AT91_CAN_MID0 0x208 // Mailbox 0 ID
2262 #define AT91_CAN_MFID0 0x20C // Mailbox 0 Family ID
2263 #define AT91_CAN_MSR0 0x210 // Mailbox 0 Status
2264 #define AT91_CAM_MSR_MDLC_MASK (0xf << 16) // Mailbox Data Length Code mask
2265 #define AT91_CAM_MSR_MDLC_SHIFT (16) // Mailbox Data Length Code shift
2266 #define AT91_CAM_MSR_MRTR (1 << 20) // Mailbox Remote Tx Request
2267 #define AT91_CAM_MSR_MABT (1 << 22) // Mailbox Abort
2268 #define AT91_CAM_MSR_MRDY (1 << 23) // Mailbox Ready
2269 #define AT91_CAM_MSR_MMI (1 << 24) // Mailbox Message Ignored
2270 #define AT91_CAN_MDL0 0x214 // Mailbox 0 Data Low
2271 #define AT91_CAN_MDH0 0x218 // Mailbox 0 Data High
2272 #define AT91_CAN_MCR0 0x21c // Mailbox 0 Control
2273 #define AT91_CAM_MCR_MDLC_MASK (0xf << 16) // Mailbox Data Length Code mask
2274 #define AT91_CAM_MCR_MDLC_SHIFT (16) // Mailbox Data Length Code shift
2275 #define AT91_CAM_MCR_MRTR (1 << 20) // Mailbox Remote Tx Request
2276 #define AT91_CAM_MCR_MACR (1 << 22) // Mailbox Abort Request
2277 #define AT91_CAM_MCR_MTCR (1 << 23) // Mailbox Transfer Command
2278 #define AT91_CAN_MMR1 0x220 // Mailbox 1 Mode
2279 #define AT91_CAN_MAM1 0x224 // Mailbox 1 Acceptance Mask
2280 #define AT91_CAN_MID1 0x228 // Mailbox 1 ID
2281 #define AT91_CAN_MFID1 0x22C // Mailbox 1 Family ID
2282 #define AT91_CAN_MSR1 0x230 // Mailbox 1 Status
2283 #define AT91_CAN_MDL1 0x234 // Mailbox 1 Data Low
2284 #define AT91_CAN_MDH1 0x238 // Mailbox 1 Data High
2285 #define AT91_CAN_MCR1 0x23c // Mailbox 1 Control
2289 //=============================================================================
2290 // Pulse Width Modulation (PWM)
2292 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
2295 #define AT91_PWM 0XFFFCC000
2296 #define AT91_PWM_CH0 0xFFFCC200
2297 #define AT91_PWM_CH1 0xFFFCC220
2298 #define AT91_PWM_CH2 0xFFFCC240
2299 #define AT91_PWM_CH3 0xFFFCC260
2300 #define AT91_PWM_CH_SIZE 0x20
2303 #if defined(CYGHWR_HAL_ARM_AT91SAM7)
2304 #define AT91_PWM_CHANNELS 4
2307 #define AT91_PWM_MR (0x00) // Mode
2308 #define AT91_PWM_MR_DIVA_MASK (0xff) // CLKA divide factor mask
2309 #define AT91_PWM_MR_DIVA_SHIFT (00) // CLKA divide factor shirt
2310 #define AT91_PWM_MR_PREA_MCK_BY_1 ( 0 << 8) // Prescale A MCLK / 1
2311 #define AT91_PWM_MR_PREA_MCK_BY_2 ( 1 << 8) // Prescale A MCLK / 2
2312 #define AT91_PWM_MR_PREA_MCK_BY_4 ( 2 << 8) // Prescale A MCLK / 4
2313 #define AT91_PWM_MR_PREA_MCK_BY_8 ( 3 << 8) // Prescale A MCLK / 8
2314 #define AT91_PWM_MR_PREA_MCK_BY_16 ( 4 << 8) // Prescale A MCLK / 16
2315 #define AT91_PWM_MR_PREA_MCK_BY_32 ( 5 << 8) // Prescale A MCLK / 32
2316 #define AT91_PWM_MR_PREA_MCK_BY_64 ( 6 << 8) // Prescale A MCLK / 64
2317 #define AT91_PWM_MR_PREA_MCK_BY_128 ( 7 << 8) // Prescale A MCLK / 128
2318 #define AT91_PWM_MR_PREA_MCK_BY_256 ( 8 << 8) // Prescale A MCLK / 256
2319 #define AT91_PWM_MR_PREA_MCK_BY_512 ( 9 << 8) // Prescale A MCLK / 512
2320 #define AT91_PWM_MR_PREA_MCK_BY_1024 (10 << 8) // Prescale A MCLK / 1024
2322 #define AT91_PWM_MR_DIVB_MASK (0xff) // CLKB divide factor mask
2323 #define AT91_PWM_MR_DIVB_SHIFT (16) // CLKB divide factor shirt
2324 #define AT91_PWM_MR_PREB_MCK_BY_1 ( 0 << 24) // Prescale B MCLK / 1
2325 #define AT91_PWM_MR_PREB_MCK_BY_2 ( 1 << 24) // Prescale B MCLK / 2
2326 #define AT91_PWM_MR_PREB_MCK_BY_4 ( 2 << 24) // Prescale B MCLK / 4
2327 #define AT91_PWM_MR_PREB_MCK_BY_8 ( 3 << 24) // Prescale B MCLK / 8
2328 #define AT91_PWM_MR_PREB_MCK_BY_16 ( 4 << 24) // Prescale B MCLK / 16
2329 #define AT91_PWM_MR_PREB_MCK_BY_32 ( 5 << 24) // Prescale B MCLK / 32
2330 #define AT91_PWM_MR_PREB_MCK_BY_64 ( 6 << 24) // Prescale B MCLK / 64
2331 #define AT91_PWM_MR_PREB_MCK_BY_128 ( 7 << 24) // Prescale B MCLK / 128
2332 #define AT91_PWM_MR_PREB_MCK_BY_256 ( 8 << 24) // Prescale B MCLK / 256
2333 #define AT91_PWM_MR_PREB_MCK_BY_512 ( 9 << 24) // Prescale B MCLK / 512
2334 #define AT91_PWM_MR_PREB_MCK_BY_1024 (10 << 24) // Prescale B MCLK / 1024
2335 #define AT91_PWM_ENA (0x04) // Enable
2336 #define AT91_PWM_CHANNEL_ID_0 (0) // Channel ID 0
2337 #define AT91_PWM_CHANNEL_ID_1 (1) // Channel ID 1
2338 #define AT91_PWM_CHANNEL_ID_2 (2) // Channel ID 2
2339 #define AT91_PWM_CHANNEL_ID_3 (3) // Channel ID 3
2340 #define AT91_PWM_CHANNEL_ID_4 (4) // Channel ID 4
2341 #define AT91_PWM_CHANNEL_ID_5 (5) // Channel ID 5
2342 #define AT91_PWM_CHANNEL_ID_6 (6) // Channel ID 6
2343 #define AT91_PWM_CHANNEL_ID_7 (7) // Channel ID 7
2344 #define AT91_PWM_DIS (0x08) // Disable
2345 #define AT91_PWM_SR (0x0c) // Status
2346 #define AT91_PWM_IER (0x10) // Interrupt Enable
2347 #define AT91_PWM_IDR (0x14) // Interrupt Disable
2348 #define AT91_PWM_IMR (0x18) // Interrupt Mask
2349 #define AT91_PWM_ISR (0x1c) // Interrupt Status
2350 #define AT91_PWM_VR (0xfc) // Version
2352 // Channel registers.
2353 #define AT91_PWM_CMR (0x00) // Channel Mode
2354 #define AT91_PWM_CMR_CPRE_MCK_BY_1 0 // Channel Prescale MCL / 1
2355 #define AT91_PWM_CMR_CPRE_MCK_BY_2 1 // Channel Prescale MCL / 2
2356 #define AT91_PWM_CMR_CPRE_MCK_BY_4 2 // Channel Prescale MCL / 4
2357 #define AT91_PWM_CMR_CPRE_MCK_BY_8 3 // Channel Prescale MCL / 8
2358 #define AT91_PWM_CMR_CPRE_MCK_BY_16 4 // Channel Prescale MCL / 16
2359 #define AT91_PWM_CMR_CPRE_MCK_BY_32 5 // Channel Prescale MCL / 32
2360 #define AT91_PWM_CMR_CPRE_MCK_BY_64 6 // Channel Prescale MCL / 64
2361 #define AT91_PWM_CMR_CPRE_MCK_BY_128 7 // Channel Prescale MCL / 128
2362 #define AT91_PWM_CMR_CPRE_MCK_BY_256 8 // Channel Prescale MCL / 256
2363 #define AT91_PWM_CMR_CPRE_MCK_BY_512 9 // Channel Prescale MCL / 512
2364 #define AT91_PWM_CMR_CPRE_MCK_BY_1024 10 // Channel Prescale MCL / 1024
2365 #define AT91_PWM_CMR_CPRE_MCK_A 11 // Channel MCLK A
2366 #define AT91_PWM_CMR_CPRE_MCK_B 12 // Channel MCLK B
2367 #define AT91_PWM_CMR_CALG_LEFT (0 << 8) // Left align period
2368 #define AT91_PWM_CMR_CALG_CENTER (1 << 8) // Center align period
2369 #define AT91_PWM_CMR_CPOL_LOW (0 << 9) // Low to start with
2370 #define AT91_PWM_CMR_CPOL_HIGH (1 << 9) // High to start with
2371 #define AT91_PWM_CPD_DUTY (0 << 10) // Notify the duty cycle
2372 #define AT91_PWM_CPD_PERIOD (1 << 10) // Notify the period
2373 #define AT91_PWM_CDTY (0x04) // Channel Duty Cycle
2374 #define AT91_PWM_CPRDR (0x08) // Channel Period
2375 #define AT91_PWM_CCNTR (0x0C) // Channel Counter
2376 #define AT91_PWM_CUPDR (0x10) // Channel Update
2380 //=============================================================================
2381 // FIQ interrupt vector which is shared by all HAL varients.
2383 #define CYGNUM_HAL_INTERRUPT_FIQ 0
2385 //=============================================================================
2386 // Macros for access the GPIO lines and configuring peripheral pins
2388 // Given a pin description, determine which PIO controller it is on
2389 #define HAL_ARM_AT91_PIO_CTRL(_pin_) \
2390 ((_pin_ >> 16) & 0xff)
2392 // Given a pin description, determine which PIO bit controls this pin
2393 #define HAL_ARM_AT91_PIO_BIT(_pin_) \
2394 (1 << (_pin_ & 0xff))
2396 // Evaluate to true if the pin is using peripheral A
2397 #define HAL_ARM_AT91_PIO_A(_pin_) \
2398 (((_pin_ >> 8) & 0xff) == 0)
2400 // Configure a peripheral pin on a specific PIO controller.
2402 #define HAL_ARM_AT91_PIOX_CFG(_pin_, _nr_, _pio_base_) \
2404 if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
2405 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PDR, \
2406 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2407 if (HAL_ARM_AT91_PIO_A(_pin_)) { \
2408 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_ASR, \
2409 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2411 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_BSR, \
2412 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2416 #else // AT91_PIO_ASR
2417 #define HAL_ARM_AT91_PIOX_CFG(_pin_, _nr_, _pio_base_) \
2419 if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
2420 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PDR, \
2421 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2424 #endif // !AT91_PIO_ASR
2426 // Configure a GPIO pin direction on a specific PIO controller.
2427 #define HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, _nr_, _pio_base_) \
2429 if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
2430 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PER, \
2431 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2432 if ((_dir_) == AT91_PIN_IN) { \
2433 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_ODR, \
2434 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2436 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_OER, \
2437 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2442 // Configure a GPIO pin pullup on a specific PIO controller.
2443 #define HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, _nr_, _pio_base_) \
2445 if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
2447 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PPUER, \
2448 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2450 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PPUDR, \
2451 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2456 // Set a GPIO pin on a specific PIO controller to generate interrupts
2457 #define HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, _nr_, _pio_base_) \
2459 if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
2461 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_IER, \
2462 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2464 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_IDR, \
2465 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2470 // Set a GPIO pin on a specific PIO controller.
2471 #define HAL_ARM_AT91_GPIOX_SET(_pin_, _nr_, _pio_base_) \
2473 if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
2474 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_SODR, \
2475 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2479 // Reset a GPIO pin on a specific PIO controller.
2480 #define HAL_ARM_AT91_GPIOX_RESET(_pin_, _nr_, _pio_base_) \
2482 if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
2483 HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_CODR, \
2484 HAL_ARM_AT91_PIO_BIT(_pin_)); \
2488 // Get a GPIO pin on a specific PIO controller.
2489 #define HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, _nr_, _pio_base_) \
2491 cyg_uint32 _pdsr_; \
2492 if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
2493 HAL_READ_UINT32((_pio_base_)+AT91_PIO_PDSR, _pdsr_); \
2494 (_value_) = (_pdsr_ & HAL_ARM_AT91_PIO_BIT(_pin_) ? 1 : 0); \
2498 #define AT91_PIN_IN 1
2499 #define AT91_PIN_OUT 0
2500 #define AT91_PIN_PULLUP_ENABLE 1
2501 #define AT91_PIN_PULLUP_DISABLE 0
2502 #define AT91_PIN_INTERRUPT_ENABLE 1
2503 #define AT91_PIN_INTERRUPT_DISABLE 0
2506 // Only one PIO controller
2508 // Configure a peripheral pin for peripheral operation
2509 #define HAL_ARM_AT91_PIO_CFG(_pin_) \
2511 HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \
2514 // Configure a GPIO pin direction
2515 #define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \
2517 HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \
2520 // Configure a GPIO pin pullup resistor
2521 #define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \
2523 HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \
2526 // Configure a GPIO pin to generate interrupts
2527 #define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \
2529 HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \
2532 // Set a GPIO pin to one
2533 #define HAL_ARM_AT91_GPIO_SET(_pin_) \
2535 HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \
2538 // Reset a GPIO pin to zero
2539 #define HAL_ARM_AT91_GPIO_RESET(_pin_) \
2541 HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \
2544 // Get the state of a GPIO pin
2545 #define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \
2547 HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \
2551 // Two PIO controllers
2553 // Configure a peripheral pin for peripheral operation
2554 #define HAL_ARM_AT91_PIO_CFG(_pin_) \
2556 HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \
2557 HAL_ARM_AT91_PIOX_CFG(_pin_, 1, AT91_PIOB); \
2560 // Configure a GPIO pin direction
2561 #define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \
2563 HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \
2564 HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 1, AT91_PIOB); \
2567 // Configure a GPIO pin pullup resistor
2568 #define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \
2570 HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \
2571 HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 1, AT91_PIOB); \
2574 // Configure a GPIO pin to generate interrupts
2575 #define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \
2577 HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \
2578 HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 1, AT91_PIOB); \
2581 // Set a GPIO pin to 1
2582 #define HAL_ARM_AT91_GPIO_SET(_pin_) \
2584 HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \
2585 HAL_ARM_AT91_GPIOX_SET(_pin_, 1, AT91_PIOB); \
2588 // Reset a GPIO pin to 0
2589 #define HAL_ARM_AT91_GPIO_RESET(_pin_) \
2591 HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \
2592 HAL_ARM_AT91_GPIOX_RESET(_pin_, 1, AT91_PIOB); \
2595 // Get the state of a GPIO pin
2596 #define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \
2598 HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \
2599 HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 1, AT91_PIOB); \
2603 // Put a GPIO pin to a given state
2604 #define HAL_ARM_AT91_GPIO_PUT(_pin_, _state_) \
2607 HAL_ARM_AT91_GPIO_SET(_pin_); \
2609 HAL_ARM_AT91_GPIO_RESET(_pin_); \
2613 //-----------------------------------------------------------------------------
2615 #endif // CYGONCE_HAL_VAR_IO_H
projects / karo-tx-redboot.git / blob