1 #ifndef CYGONCE_HAL_VAR_IO_H
2 #define CYGONCE_HAL_VAR_IO_H
3 //=============================================================================
7 // Variant specific registers
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors:jskov, gthomas, tkoeller, tdrury, nickg
49 // Purpose: AT91 variant specific registers
51 // Usage: #include <cyg/hal/var_io.h>
53 //####DESCRIPTIONEND####
55 //=============================================================================
57 #include <cyg/hal/plf_io.h>
59 //=============================================================================
63 #define AT91_USART0 0xFFFD0000
67 #define AT91_USART1 0xFFFCC000
70 #define AT91_US_CR 0x00 // Control register
71 #define AT91_US_CR_RxRESET (1<<2)
72 #define AT91_US_CR_TxRESET (1<<3)
73 #define AT91_US_CR_RxENAB (1<<4)
74 #define AT91_US_CR_RxDISAB (1<<5)
75 #define AT91_US_CR_TxENAB (1<<6)
76 #define AT91_US_CR_TxDISAB (1<<7)
77 #define AT91_US_CR_RSTATUS (1<<8)
78 #define AT91_US_CR_STTTO (1<<11)
79 #define AT91_US_MR 0x04 // Mode register
80 #define AT91_US_MR_CLOCK 4
81 #define AT91_US_MR_CLOCK_MCK (0<<AT91_US_MR_CLOCK)
82 #define AT91_US_MR_CLOCK_MCK8 (1<<AT91_US_MR_CLOCK)
83 #define AT91_US_MR_CLOCK_SCK (2<<AT91_US_MR_CLOCK)
84 #define AT91_US_MR_LENGTH 6
85 #define AT91_US_MR_LENGTH_5 (0<<AT91_US_MR_LENGTH)
86 #define AT91_US_MR_LENGTH_6 (1<<AT91_US_MR_LENGTH)
87 #define AT91_US_MR_LENGTH_7 (2<<AT91_US_MR_LENGTH)
88 #define AT91_US_MR_LENGTH_8 (3<<AT91_US_MR_LENGTH)
89 #define AT91_US_MR_SYNC 8
90 #define AT91_US_MR_SYNC_ASYNC (0<<AT91_US_MR_SYNC)
91 #define AT91_US_MR_SYNC_SYNC (1<<AT91_US_MR_SYNC)
92 #define AT91_US_MR_PARITY 9
93 #define AT91_US_MR_PARITY_EVEN (0<<AT91_US_MR_PARITY)
94 #define AT91_US_MR_PARITY_ODD (1<<AT91_US_MR_PARITY)
95 #define AT91_US_MR_PARITY_SPACE (2<<AT91_US_MR_PARITY)
96 #define AT91_US_MR_PARITY_MARK (3<<AT91_US_MR_PARITY)
97 #define AT91_US_MR_PARITY_NONE (4<<AT91_US_MR_PARITY)
98 #define AT91_US_MR_PARITY_MULTI (6<<AT91_US_MR_PARITY)
99 #define AT91_US_MR_STOP 12
100 #define AT91_US_MR_STOP_1 (0<<AT91_US_MR_STOP)
101 #define AT91_US_MR_STOP_1_5 (1<<AT91_US_MR_STOP)
102 #define AT91_US_MR_STOP_2 (2<<AT91_US_MR_STOP)
103 #define AT91_US_MR_MODE 14
104 #define AT91_US_MR_MODE_NORMAL (0<<AT91_US_MR_MODE)
105 #define AT91_US_MR_MODE_ECHO (1<<AT91_US_MR_MODE)
106 #define AT91_US_MR_MODE_LOCAL (2<<AT91_US_MR_MODE)
107 #define AT91_US_MR_MODE_REMOTE (3<<AT91_US_MR_MODE)
108 #define AT91_US_MR_MODE9 17
109 #define AT91_US_MR_CLKO 18
110 #define AT91_US_IER 0x08 // Interrupt enable register
111 #define AT91_US_IER_RxRDY (1<<0) // Receive data ready
112 #define AT91_US_IER_TxRDY (1<<1) // Transmitter ready
113 #define AT91_US_IER_RxBRK (1<<2) // Break received
114 #define AT91_US_IER_ENDRX (1<<3) // Rx end
115 #define AT91_US_IER_ENDTX (1<<4) // Tx end
116 #define AT91_US_IER_OVRE (1<<5) // Rx overflow
117 #define AT91_US_IER_FRAME (1<<6) // Rx framing error
118 #define AT91_US_IER_PARITY (1<<7) // Rx parity
119 #define AT91_US_IER_TIMEOUT (1<<8) // Rx timeout
120 #define AT91_US_IER_TxEMPTY (1<<9) // Tx empty
121 #define AT91_US_IDR 0x0C // Interrupt disable register
122 #define AT91_US_IMR 0x10 // Interrupt mask register
123 #define AT91_US_CSR 0x14 // Channel status register
124 #define AT91_US_CSR_RxRDY 0x01 // Receive data ready
125 #define AT91_US_CSR_TxRDY 0x02 // Transmit ready
126 #define AT91_US_CSR_RXBRK 0x04 // Transmit ready
127 #define AT91_US_CSR_ENDRX 0x08 // Transmit ready
128 #define AT91_US_CSR_ENDTX 0x10 // Transmit ready
129 #define AT91_US_CSR_OVRE 0x20 // Overrun error
130 #define AT91_US_CSR_FRAME 0x40 // Framing error
131 #define AT91_US_CSR_TIMEOUT 0x80 // Timeout
132 #define AT91_US_RHR 0x18 // Receive holding register
133 #define AT91_US_THR 0x1C // Transmit holding register
134 #define AT91_US_BRG 0x20 // Baud rate generator
135 #define AT91_US_RTO 0x24 // Receive time out
136 #define AT91_US_TTG 0x28 // Transmit timer guard
138 // PDC US registers may have different addresses in at91 targets (i.e jtst)
140 #define AT91_US_RPR 0x30 // Receive pointer register
144 #define AT91_US_RCR 0x34 // Receive counter register
148 #define AT91_US_TPR 0x38 // Transmit pointer register
152 #define AT91_US_TCR 0x3c // Transmit counter register
155 // macro could be different from target to target (i.e jtst)
157 #define AT91_US_BAUD(baud) ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(8*(baud))+1)/2)
159 //=============================================================================
163 #define AT91_PIO 0xFFFF0000
166 #define AT91_PIO_PER 0x00 // PIO enable
167 #define AT91_PIO_PDR 0x04 // PIO disable
168 #define AT91_PIO_PSR 0x08 // PIO status
170 #if defined(CYGHWR_HAL_ARM_AT91_M55800A)
173 #define AT91_PIO_PSR_TCLK3 0x00000001 // Timer 3 Clock signal
174 #define AT91_PIO_PSR_TIOA3 0x00000002 // Timer 3 Signal A
175 #define AT91_PIO_PSR_TIOB3 0x00000004 // Timer 3 Signal B
176 #define AT91_PIO_PSR_TCLK4 0x00000008 // Timer 4 Clock signal
177 #define AT91_PIO_PSR_TIOA4 0x00000010 // Timer 4 Signal A
178 #define AT91_PIO_PSR_TIOB4 0x00000020 // Timer 4 Signal B
179 #define AT91_PIO_PSR_TCLK5 0x00000040 // Timer 5 Clock signal
180 #define AT91_PIO_PSR_TIOA5 0x00000080 // Timer 5 Signal A
181 #define AT91_PIO_PSR_TIOB5 0x00000100 // Timer 5 Signal B
182 #define AT91_PIO_PSR_IRQ0 0x00000200 // External Interrupt 0
183 #define AT91_PIO_PSR_IRQ1 0x00000400 // External Interrupt 1
184 #define AT91_PIO_PSR_IRQ2 0x00000800 // External Interrupt 2
185 #define AT91_PIO_PSR_IRQ3 0x00001000 // External Interrupt 3
186 #define AT91_PIO_PSR_FIQ 0x00002000 // Fast Interrupt
187 #define AT91_PIO_PSR_SCK0 0x00004000 // USART 0 Clock signal
188 #define AT91_PIO_PSR_TXD0 0x00008000 // USART 0 transmit data
189 #define AT91_PIO_PSR_RXD0 0x00010000 // USART 0 receive data
190 #define AT91_PIO_PSR_SCK1 0x00020000 // USART 1 Clock signal
191 #define AT91_PIO_PSR_TXD1 0x00040000 // USART 1 transmit data
192 #define AT91_PIO_PSR_RXD1 0x00080000 // USART 1 receive data
193 #define AT91_PIO_PSR_SCK2 0x00100000 // USART 2 Clock signal
194 #define AT91_PIO_PSR_TXD2 0x00200000 // USART 2 transmit data
195 #define AT91_PIO_PSR_RXD2 0x00400000 // USART 2 receive data
196 #define AT91_PIO_PSR_SPCK 0x00800000 // SPI Clock signal
197 #define AT91_PIO_PSR_MISO 0x01000000 // SPI Master In Slave Out
198 #define AT91_PIO_PSR_MOIS 0x02000000 // SPI Master Out Slave In
199 #define AT91_PIO_PSR_NPCS0 0x04000000 // SPI Peripheral Chip Select 0
200 #define AT91_PIO_PSR_NPCS1 0x08000000 // SPI Peripheral Chip Select 1
201 #define AT91_PIO_PSR_NPCS2 0x10000000 // SPI Peripheral Chip Select 2
202 #define AT91_PIO_PSR_NPCS3 0x20000000 // SPI Peripheral Chip Select 3
205 #define AT91_PIO_PSR_IRQ4 0x00000008 // External Interrupt 4
206 #define AT91_PIO_PSR_IRQ5 0x00000010 // External Interrupt 5
207 #define AT91_PIO_PSR_AD0TRIG 0x00000040 // ADC0 External Trigger
208 #define AT91_PIO_PSR_AD1TRIG 0x00000080 // ADC1 External Trigger
209 #define AT91_PIO_PSR_BMS 0x00040000 // Boot Mode Select
210 #define AT91_PIO_PSR_TCLK0 0x00080000 // Timer 0 Clock signal
211 #define AT91_PIO_PSR_TIOA0 0x00100000 // Timer 0 Signal A
212 #define AT91_PIO_PSR_TIOB0 0x00200000 // Timer 0 Signal B
213 #define AT91_PIO_PSR_TCLK1 0x00400000 // Timer 1 Clock signal
214 #define AT91_PIO_PSR_TIOA1 0x00800000 // Timer 1 Signal A
215 #define AT91_PIO_PSR_TIOB1 0x01000000 // Timer 1 Signal B
216 #define AT91_PIO_PSR_TCLK2 0x02000000 // Timer 2 Clock signal
217 #define AT91_PIO_PSR_TIOA2 0x04000000 // Timer 2 Signal A
218 #define AT91_PIO_PSR_TIOB2 0x08000000 // Timer 2 Signal B
222 #define AT91_PIO_PSR_TCLK0 0x00000001 // Timer #0 clock
223 #define AT91_PIO_PSR_TIOA0 0x00000002 // Timer #0 signal A
224 #define AT91_PIO_PSR_TIOB0 0x00000004 // Timer #0 signal B
225 #define AT91_PIO_PSR_TCLK1 0x00000008 // Timer #1 clock
226 #define AT91_PIO_PSR_TIOA1 0x00000010 // Timer #1 signal A
227 #define AT91_PIO_PSR_TIOB1 0x00000020 // Timer #1 signal B
228 #define AT91_PIO_PSR_TCLK2 0x00000040 // Timer #2 clock
229 #define AT91_PIO_PSR_TIOA2 0x00000080 // Timer #2 signal A
230 #define AT91_PIO_PSR_TIOB2 0x00000100 // Timer #2 signal B
231 #define AT91_PIO_PSR_IRQ0 0x00000200 // IRQ #0
232 #define AT91_PIO_PSR_IRQ1 0x00000400 // IRQ #1
233 #define AT91_PIO_PSR_IRQ2 0x00000800 // IRQ #2
234 #define AT91_PIO_PSR_FIQ 0x00001000 // FIQ
235 #define AT91_PIO_PSR_SCK0 0x00002000 // Serial port #0 clock
236 #define AT91_PIO_PSR_TXD0 0x00004000 // Serial port #0 TxD
237 #define AT91_PIO_PSR_RXD0 0x00008000 // Serial port #0 RxD
238 #define AT91_PIO_PSR_P16 0x00010000 // PIO port #16
239 #define AT91_PIO_PSR_P17 0x00020000 // PIO port #17
240 #define AT91_PIO_PSR_P18 0x00040000 // PIO port #18
241 #define AT91_PIO_PSR_P19 0x00080000 // PIO port #19
242 #define AT91_PIO_PSR_SCK1 0x00100000 // Serial port #1 clock
243 #define AT91_PIO_PSR_TXD1 0x00200000 // Serial port #1 TxD
244 #define AT91_PIO_PSR_RXD1 0x00400000 // Serial port #1 RxD
245 #define AT91_PIO_PSR_P23 0x00800000 // PIO port #23
246 #define AT91_PIO_PSR_P24 0x01000000 // PIO port #24
247 #define AT91_PIO_PSR_MCKO 0x02000000 // Master clock out
248 #define AT91_PIO_PSR_NCS2 0x04000000 // Chip select #2
249 #define AT91_PIO_PSR_NCS3 0x08000000 // Chip select #3
250 #define AT91_PIO_PSR_CS7_A20 0x10000000 // Chip select #7 or A20
251 #define AT91_PIO_PSR_CS6_A21 0x20000000 // Chip select #6 or A21
252 #define AT91_PIO_PSR_CS5_A22 0x40000000 // Chip select #5 or A22
253 #define AT91_PIO_PSR_CS4_A23 0x80000000 // Chip select #4 or A23
257 #define AT91_PIO_OER 0x10 // Output enable
258 #define AT91_PIO_ODR 0x14 // Output disable
259 #define AT91_PIO_OSR 0x18 // Output status
260 #define AT91_PIO_IFER 0x20 // Input Filter enable
261 #define AT91_PIO_IFDR 0x24 // Input Filter disable
262 #define AT91_PIO_IFSR 0x28 // Input Filter status
263 #define AT91_PIO_SODR 0x30 // Set out bits
264 #define AT91_PIO_CODR 0x34 // Clear out bits
265 #define AT91_PIO_ODSR 0x38 // Output data status
266 #define AT91_PIO_PDSR 0x3C // Pin data status
267 #define AT91_PIO_IER 0x40 // Interrupt enable
268 #define AT91_PIO_IDR 0x44 // Interrupt disable
269 #define AT91_PIO_IMR 0x48 // Interrupt mask
270 #define AT91_PIO_ISR 0x4C // Interrupt status
272 //=============================================================================
273 // Advanced Interrupt Controller (AIC)
276 #define AT91_AIC 0xFFFFF000
279 #define AT91_AIC_SMR0 ((0*4)+0x000)
280 #define AT91_AIC_SMR1 ((1*4)+0x000)
281 #define AT91_AIC_SMR2 ((2*4)+0x000)
282 #define AT91_AIC_SMR3 ((3*4)+0x000)
283 #define AT91_AIC_SMR4 ((4*4)+0x000)
284 #define AT91_AIC_SMR5 ((5*4)+0x000)
285 #define AT91_AIC_SMR6 ((6*4)+0x000)
286 #define AT91_AIC_SMR7 ((7*4)+0x000)
287 #define AT91_AIC_SMR8 ((8*4)+0x000)
288 #define AT91_AIC_SMR9 ((9*4)+0x000)
289 #define AT91_AIC_SMR10 ((10*4)+0x000)
290 #define AT91_AIC_SMR11 ((11*4)+0x000)
291 #define AT91_AIC_SMR12 ((12*4)+0x000)
292 #define AT91_AIC_SMR13 ((13*4)+0x000)
293 #define AT91_AIC_SMR14 ((14*4)+0x000)
294 #define AT91_AIC_SMR15 ((15*4)+0x000)
295 #define AT91_AIC_SMR16 ((16*4)+0x000)
296 #define AT91_AIC_SMR17 ((17*4)+0x000)
297 #define AT91_AIC_SMR18 ((18*4)+0x000)
298 #define AT91_AIC_SMR19 ((19*4)+0x000)
299 #define AT91_AIC_SMR20 ((20*4)+0x000)
300 #define AT91_AIC_SMR21 ((21*4)+0x000)
301 #define AT91_AIC_SMR22 ((22*4)+0x000)
302 #define AT91_AIC_SMR23 ((23*4)+0x000)
303 #define AT91_AIC_SMR24 ((24*4)+0x000)
304 #define AT91_AIC_SMR25 ((25*4)+0x000)
305 #define AT91_AIC_SMR26 ((26*4)+0x000)
306 #define AT91_AIC_SMR27 ((27*4)+0x000)
307 #define AT91_AIC_SMR28 ((28*4)+0x000)
308 #define AT91_AIC_SMR29 ((29*4)+0x000)
309 #define AT91_AIC_SMR30 ((30*4)+0x000)
310 #define AT91_AIC_SMR31 ((31*4)+0x000)
311 #define AT91_AIC_SMR_LEVEL_LOW (0<<5)
312 #define AT91_AIC_SMR_LEVEL_HI (2<<5)
313 #define AT91_AIC_SMR_EDGE_NEG (1<<5)
314 #define AT91_AIC_SMR_EDGE_POS (3<<5)
315 #define AT91_AIC_SMR_PRIORITY 0x07
316 #define AT91_AIC_SVR0 ((0*4)+0x080)
317 #define AT91_AIC_SVR1 ((1*4)+0x080)
318 #define AT91_AIC_SVR2 ((2*4)+0x080)
319 #define AT91_AIC_SVR3 ((3*4)+0x080)
320 #define AT91_AIC_SVR4 ((4*4)+0x080)
321 #define AT91_AIC_SVR5 ((5*4)+0x080)
322 #define AT91_AIC_SVR6 ((6*4)+0x080)
323 #define AT91_AIC_SVR7 ((7*4)+0x080)
324 #define AT91_AIC_SVR8 ((8*4)+0x080)
325 #define AT91_AIC_SVR9 ((9*4)+0x080)
326 #define AT91_AIC_SVR10 ((10*4)+0x080)
327 #define AT91_AIC_SVR11 ((11*4)+0x080)
328 #define AT91_AIC_SVR12 ((12*4)+0x080)
329 #define AT91_AIC_SVR13 ((13*4)+0x080)
330 #define AT91_AIC_SVR14 ((14*4)+0x080)
331 #define AT91_AIC_SVR15 ((15*4)+0x080)
332 #define AT91_AIC_SVR16 ((16*4)+0x080)
333 #define AT91_AIC_SVR17 ((17*4)+0x080)
334 #define AT91_AIC_SVR18 ((18*4)+0x080)
335 #define AT91_AIC_SVR19 ((19*4)+0x080)
336 #define AT91_AIC_SVR20 ((20*4)+0x080)
337 #define AT91_AIC_SVR21 ((21*4)+0x080)
338 #define AT91_AIC_SVR22 ((22*4)+0x080)
339 #define AT91_AIC_SVR23 ((23*4)+0x080)
340 #define AT91_AIC_SVR24 ((24*4)+0x080)
341 #define AT91_AIC_SVR25 ((25*4)+0x080)
342 #define AT91_AIC_SVR26 ((26*4)+0x080)
343 #define AT91_AIC_SVR27 ((27*4)+0x080)
344 #define AT91_AIC_SVR28 ((28*4)+0x080)
345 #define AT91_AIC_SVR29 ((29*4)+0x080)
346 #define AT91_AIC_SVR30 ((30*4)+0x080)
347 #define AT91_AIC_SVR31 ((31*4)+0x080)
348 #define AT91_AIC_IVR 0x100
349 #define AT91_AIC_FVR 0x104
350 #define AT91_AIC_ISR 0x108
351 #define AT91_AIC_IPR 0x10C
352 #define AT91_AIC_IMR 0x110
353 #define AT91_AIC_CISR 0x114
354 #define AT91_AIC_IECR 0x120
355 #define AT91_AIC_IDCR 0x124
356 #define AT91_AIC_ICCR 0x128
357 #define AT91_AIC_ISCR 0x12C
358 #define AT91_AIC_EOI 0x130
359 #define AT91_AIC_SVR 0x134
361 //=============================================================================
365 #define AT91_TC 0xFFFE0000
368 #define AT91_TC_TC0 0x00
369 #define AT91_TC_CCR 0x00
370 #define AT91_TC_CCR_CLKEN 0x01
371 #define AT91_TC_CCR_CLKDIS 0x02
372 #define AT91_TC_CCR_TRIG 0x04
373 // Channel Mode Register
374 #define AT91_TC_CMR 0x04
375 #define AT91_TC_CMR_CLKS 0
376 #define AT91_TC_CMR_CLKS_MCK2 (0<<0)
377 #define AT91_TC_CMR_CLKS_MCK8 (1<<0)
378 #define AT91_TC_CMR_CLKS_MCK32 (2<<0)
379 #define AT91_TC_CMR_CLKS_MCK128 (3<<0)
380 #define AT91_TC_CMR_CLKS_MCK1024 (4<<0)
381 #define AT91_TC_CMR_CLKS_XC0 (5<<0)
382 #define AT91_TC_CMR_CLKS_XC1 (6<<0)
383 #define AT91_TC_CMR_CLKS_XC2 (7<<0)
384 #define AT91_TC_CMR_CLKI (1<<3)
385 #define AT91_TC_CMR_BURST_NONE (0<<4)
386 #define AT91_TC_CMR_BURST_XC0 (1<<4)
387 #define AT91_TC_CMR_BURST_XC1 (2<<4)
388 #define AT91_TC_CMR_BURST_XC2 (3<<4)
389 // Capture mode definitions
390 #define AT91_TC_CMR_LDBSTOP (1<<6)
391 #define AT91_TC_CMR_LDBDIS (1<<7)
392 #define AT91_TC_CMR_TRIG_NONE (0<<8)
393 #define AT91_TC_CMR_TRIG_NEG (1<<8)
394 #define AT91_TC_CMR_TRIG_POS (2<<8)
395 #define AT91_TC_CMR_TRIG_BOTH (3<<8)
396 #define AT91_TC_CMR_EXT_TRIG_TIOB (0<<10)
397 #define AT91_TC_CMR_EXT_TRIG_TIOA (1<<10)
398 #define AT91_TC_CMR_CPCTRG (1<<14)
399 #define AT91_TC_CMR_LDRA_NONE (0<<16)
400 #define AT91_TC_CMR_LDRA_TIOA_NEG (1<<16)
401 #define AT91_TC_CMR_LDRA_TIOA_POS (2<<16)
402 #define AT91_TC_CMR_LDRA_TIOA_BOTH (3<<16)
403 #define AT91_TC_CMR_LDRB_NONE (0<<18)
404 #define AT91_TC_CMR_LDRB_TIOA_NEG (1<<18)
405 #define AT91_TC_CMR_LDRB_TIOA_POS (2<<18)
406 #define AT91_TC_CMR_LDRB_TIOA_BOTH (3<<18)
407 // Waveform mode definitions
408 #define AT91_TC_CMR_CPCSTOP (1<<6)
409 #define AT91_TC_CMR_CPCDIS (1<<7)
410 #define AT91_TC_CMR_EEVTEDG_NONE (0<<8)
411 #define AT91_TC_CMR_EEVTEDG_NEG (1<<8)
412 #define AT91_TC_CMR_EEVTEDG_POS (2<<8)
413 #define AT91_TC_CMR_EEVTEDG_BOTH (3<<8)
414 #define AT91_TC_CMR_EEVT_TIOB (0<<10)
415 #define AT91_TC_CMR_EEVT_XC0 (1<<10)
416 #define AT91_TC_CMR_EEVT_XC1 (2<<10)
417 #define AT91_TC_CMR_EEVT_XC2 (3<<10)
418 #define AT91_TC_CMR_ENETRG (1<<12)
419 #define AT91_TC_CMR_CPCTRG (1<<14)
420 #define AT91_TC_CMR_WAVE (1<<15)
421 #define AT91_TC_CMR_ACPA_NONE (0<<16)
422 #define AT91_TC_CMR_ACPA_SET (1<<16)
423 #define AT91_TC_CMR_ACPA_CLEAR (2<<16)
424 #define AT91_TC_CMR_ACPA_TOGGLE (3<<16)
425 #define AT91_TC_CMR_ACPC_NONE (0<<18)
426 #define AT91_TC_CMR_ACPC_SET (1<<18)
427 #define AT91_TC_CMR_ACPC_CLEAR (2<<18)
428 #define AT91_TC_CMR_ACPC_TOGGLE (3<<18)
429 #define AT91_TC_CMR_AEEVT_NONE (0<<20)
430 #define AT91_TC_CMR_AEEVT_SET (1<<20)
431 #define AT91_TC_CMR_AEEVT_CLEAR (2<<20)
432 #define AT91_TC_CMR_AEEVT_TOGGLE (3<<20)
433 #define AT91_TC_CMR_ASWTRG_NONE (0<<22)
434 #define AT91_TC_CMR_ASWTRG_SET (1<<22)
435 #define AT91_TC_CMR_ASWTRG_CLEAR (2<<22)
436 #define AT91_TC_CMR_ASWTRG_TOGGLE (3<<22)
437 #define AT91_TC_CMR_BCPB_NONE (0<<24)
438 #define AT91_TC_CMR_BCPB_SET (1<<24)
439 #define AT91_TC_CMR_BCPB_CLEAR (2<<24)
440 #define AT91_TC_CMR_BCPB_TOGGLE (3<<24)
441 #define AT91_TC_CMR_BCPC_NONE (0<<26)
442 #define AT91_TC_CMR_BCPC_SET (1<<26)
443 #define AT91_TC_CMR_BCPC_CLEAR (2<<26)
444 #define AT91_TC_CMR_BCPC_TOGGLE (3<<26)
445 #define AT91_TC_CMR_BEEVT_NONE (0<<28)
446 #define AT91_TC_CMR_BEEVT_SET (1<<28)
447 #define AT91_TC_CMR_BEEVT_CLEAR (2<<28)
448 #define AT91_TC_CMR_BEEVT_TOGGLE (3<<28)
449 #define AT91_TC_CMR_BSWTRG_NONE (0<<30)
450 #define AT91_TC_CMR_BSWTRG_SET (1<<30)
451 #define AT91_TC_CMR_BSWTRG_CLEAR (2<<30)
452 #define AT91_TC_CMR_BSWTRG_TOGGLE (3<<30)
454 #define AT91_TC_CV 0x10
455 #define AT91_TC_RA 0x14
456 #define AT91_TC_RB 0x18
457 #define AT91_TC_RC 0x1C
458 #define AT91_TC_SR 0x20
459 #define AT91_TC_SR_COVF (1<<0) // Counter overrun
460 #define AT91_TC_SR_LOVR (1<<1) // Load overrun
461 #define AT91_TC_SR_CPA (1<<2) // RA compare
462 #define AT91_TC_SR_CPB (1<<3) // RB compare
463 #define AT91_TC_SR_CPC (1<<4) // RC compare
464 #define AT91_TC_SR_LDRA (1<<5) // Load A status
465 #define AT91_TC_SR_LDRB (1<<6) // Load B status
466 #define AT91_TC_SR_EXT (1<<7) // External trigger
467 #define AT91_TC_SR_CLKSTA (1<<16) // Clock enable/disable status
468 #define AT91_TC_SR_MTIOA (1<<17) // TIOA mirror
469 #define AT91_TC_SR_MTIOB (1<<18) // TIOB mirror
470 #define AT91_TC_IER 0x24
471 #define AT91_TC_IER_COVF (1<<0) // Counter overrun
472 #define AT91_TC_IER_LOVR (1<<1) // Load overrun
473 #define AT91_TC_IER_CPA (1<<2) // RA compare
474 #define AT91_TC_IER_CPB (1<<3) // RB compare
475 #define AT91_TC_IER_CPC (1<<4) // RC compare
476 #define AT91_TC_IER_LDRA (1<<5) // Load A status
477 #define AT91_TC_IER_LDRB (1<<6) // Load B status
478 #define AT91_TC_IER_EXT (1<<7) // External trigger
479 #define AT91_TC_IDR 0x28
480 #define AT91_TC_IMR 0x2C
481 #define AT91_TC_TC1 0x40
482 #define AT91_TC_TC2 0x80
483 #define AT91_TC_BCR 0xC0
484 #define AT91_TC_BCR_SYNC 0x01
485 #define AT91_TC_BMR 0xC4
487 //=============================================================================
488 // External Bus Interface
491 #define AT91_EBI 0xFFE00000
494 #define AT91_EBI_CSR0 0x00
495 #define AT91_EBI_CSR1 0x04
496 #define AT91_EBI_CSR2 0x08
497 #define AT91_EBI_CSR3 0x0C
498 #define AT91_EBI_CSR4 0x10
499 #define AT91_EBI_CSR5 0x14
500 #define AT91_EBI_CSR6 0x18
501 #define AT91_EBI_CSR7 0x1C // Chip select
502 #define AT91_EBI_CSR_DBW_16 0x1 // Data bus 16 bits wide
503 #define AT91_EBI_CSR_DBW_8 0x2 // Data bus 8 bits wide
504 #define AT91_EBI_CSR_NWS_1 (0x0 << 2)
505 #define AT91_EBI_CSR_NWS_2 (0x1 << 2)
506 #define AT91_EBI_CSR_NWS_3 (0x2 << 2)
507 #define AT91_EBI_CSR_NWS_4 (0x3 << 2)
508 #define AT91_EBI_CSR_NWS_5 (0x4 << 2)
509 #define AT91_EBI_CSR_NWS_6 (0x5 << 2)
510 #define AT91_EBI_CSR_NWS_7 (0x6 << 2)
511 #define AT91_EBI_CSR_NWS_8 (0x7 << 2) // Number of wait states
512 #define AT91_EBI_CSR_WSE (0x1 << 5) // Wait state enable
513 #define AT91_EBI_CSR_PAGES_1M (0x0 << 7)
514 #define AT91_EBI_CSR_PAGES_4M (0x1 << 7)
515 #define AT91_EBI_CSR_PAGES_16M (0x2 << 7)
516 #define AT91_EBI_CSR_PAGES_64M (0x3 << 7) // Page size
517 #define AT91_EBI_CSR_TDF_0 (0x0 << 9)
518 #define AT91_EBI_CSR_TDF_1 (0x1 << 9)
519 #define AT91_EBI_CSR_TDF_2 (0x2 << 9)
520 #define AT91_EBI_CSR_TDF_3 (0x3 << 9)
521 #define AT91_EBI_CSR_TDF_4 (0x4 << 9)
522 #define AT91_EBI_CSR_TDF_5 (0x5 << 9)
523 #define AT91_EBI_CSR_TDF_6 (0x6 << 9)
524 #define AT91_EBI_CSR_TDF_7 (0x7 << 9) // Data float output time
525 #define AT91_EBI_CSR_BAT (0x1 << 12) // Byte access type
526 #define AT91_EBI_CSR_CSEN (0x1 << 13) // Chip select enable
527 #define AT91_EBI_CSR_BA (0xFFF << 20) // Base address
528 #define AT91_EBI_RCR 0x20 // Reset control
529 #define AT91_EBI_RCR_RCB 0x1 // Remap command bit
530 #define AT91_EBI_MCR 0x24 // Memory control
531 #define AT91_EBI_MCR_ALE_16M 0x0
532 #define AT91_EBI_MCR_ALE_8M 0x4
533 #define AT91_EBI_MCR_ALE_4M 0x5
534 #define AT91_EBI_MCR_ALE_2M 0x6
535 #define AT91_EBI_MCR_ALE_1M 0x7 // Address line enable
536 #define AT91_EBI_MCR_DRP (0x1 << 4) // Data read protocol
539 //=============================================================================
540 // Power Saving or Management
542 #if defined(CYGHWR_HAL_ARM_AT91_R40807) || \
543 defined(CYGHWR_HAL_ARM_AT91_R40008)
548 #define AT91_PS 0xFFFF4000
551 #define AT91_PS_CR 0x000 // Control
552 #define AT91_PS_CR_CPU (1<<0) // Disable CPU clock (idle mode)
553 #define AT91_PS_PCER 0x004 // Peripheral clock enable
554 #define AT91_PS_PCDR 0x008 // Peripheral clock disable
555 #define AT91_PS_PCSR 0x00c // Peripheral clock status
557 #elif defined(CYGHWR_HAL_ARM_AT91_M42800A) || \
558 defined(CYGHWR_HAL_ARM_AT91_M55800A)
560 // (Advanced) Power Management
563 #define AT91_PMC 0xFFFF4000
566 #define AT91_PMC_SCER 0x00
567 #define AT91_PMC_SCDR 0x04
568 #define AT91_PMC_SCSR 0x08
570 #define AT91_PMC_PCER 0x10
571 #define AT91_PMC_PCDR 0x14
572 #define AT91_PMC_PCSR 0x18
574 #define AT91_PMC_CGMR 0x20
576 #define AT91_PMC_SR 0x30
577 #define AT91_PMC_IER 0x34
578 #define AT91_PMC_IDR 0x38
579 #define AT91_PMC_IMR 0x3c
581 #if defined(CYGHWR_HAL_ARM_AT91_M42800A)
583 #define AT91_PMC_PCER_US0 (1<<2)
584 #define AT91_PMC_PCER_US1 (1<<3)
585 #define AT91_PMC_PCER_SPIA (1<<4)
586 #define AT91_PMC_PCER_SPIB (1<<5)
587 #define AT91_PMC_PCER_TC0 (1<<6)
588 #define AT91_PMC_PCER_TC1 (1<<7)
589 #define AT91_PMC_PCER_TC2 (1<<8)
590 #define AT91_PMC_PCER_TC3 (1<<9)
591 #define AT91_PMC_PCER_TC4 (1<<10)
592 #define AT91_PMC_PCER_TC5 (1<<11)
593 #define AT91_PMC_PCER_PIOA (1<<13)
594 #define AT91_PMC_PCER_PIOB (1<<14)
596 #define AT91_PMC_CGMR_PRES_NONE 0
597 #define AT91_PMC_CGMR_PRES_DIV2 1
598 #define AT91_PMC_CGMR_PRES_DIV4 2
599 #define AT91_PMC_CGMR_PRES_DIV8 3
600 #define AT91_PMC_CGMR_PRES_DIV16 4
601 #define AT91_PMC_CGMR_PRES_DIV32 5
602 #define AT91_PMC_CGMR_PRES_DIV64 6
603 #define AT91_PMC_CGMR_PRES_RES 7
604 #define AT91_PMC_CGMR_PLLA 0x00
605 #define AT91_PMC_CGMR_PLLB 0x08
606 #define AT91_PMC_CGMR_MCK_SLCK (0<<4)
607 #define AT91_PMC_CGMR_MCK_MCK (1<<4)
608 #define AT91_PMC_CGMR_MCK_MCKINV (2<<4)
609 #define AT91_PMC_CGMR_MCK_MCKD2 (3<<4)
610 #define AT91_PMC_CGMR_MCKO_ENA (0<<6)
611 #define AT91_PMC_CGMR_MCKO_DIS (1<<6)
612 #define AT91_PMC_CGMR_CSS_SLCK (0<<7)
613 #define AT91_PMC_CGMR_CSS_PLL (1<<7)
615 #define AT91_PMC_CGMR_PLL_MUL(x) ((x)<<8)
616 #define AT91_PMC_CGMR_PLL_CNT(x) ((x)<<24)
618 #define AT91_PMC_SR_LOCK 0x01
620 #elif defined(CYGHWR_HAL_ARM_AT91_M55800A)
622 #define AT91_PMC_PCER_US0 (1<<2)
623 #define AT91_PMC_PCER_US1 (1<<3)
624 #define AT91_PMC_PCER_US2 (1<<4)
625 #define AT91_PMC_PCER_SPI (1<<5)
626 #define AT91_PMC_PCER_TC0 (1<<6)
627 #define AT91_PMC_PCER_TC1 (1<<7)
628 #define AT91_PMC_PCER_TC2 (1<<8)
629 #define AT91_PMC_PCER_TC3 (1<<9)
630 #define AT91_PMC_PCER_TC4 (1<<10)
631 #define AT91_PMC_PCER_TC5 (1<<11)
632 #define AT91_PMC_PCER_PIOA (1<<13)
633 #define AT91_PMC_PCER_PIOB (1<<14)
634 #define AT91_PMC_PCER_ADC0 (1<<15)
635 #define AT91_PMC_PCER_ADC1 (1<<16)
636 #define AT91_PMC_PCER_DAC0 (1<<17)
637 #define AT91_PMC_PCER_DAC1 (1<<18)
639 #define AT91_PMC_CGMR_MOSC_XTAL 0
640 #define AT91_PMC_CGMR_MOSC_BYP 1
641 #define AT91_PMC_CGMR_MOSC_DIS (0<<1)
642 #define AT91_PMC_CGMR_MOSC_ENA (1<<1)
643 #define AT91_PMC_CGMR_MCKO_ENA (0<<2)
644 #define AT91_PMC_CGMR_MCKO_DIS (1<<2)
645 #define AT91_PMC_CGMR_PRES_NONE (0<<4)
646 #define AT91_PMC_CGMR_PRES_DIV2 (1<<4)
647 #define AT91_PMC_CGMR_PRES_DIV4 (2<<4)
648 #define AT91_PMC_CGMR_PRES_DIV8 (3<<4)
649 #define AT91_PMC_CGMR_PRES_DIV16 (4<<4)
650 #define AT91_PMC_CGMR_PRES_DIV32 (5<<4)
651 #define AT91_PMC_CGMR_PRES_DIV64 (6<<4)
652 #define AT91_PMC_CGMR_PRES_RES (7<<4)
653 #define AT91_PMC_CGMR_CSS_LF (0<<14)
654 #define AT91_PMC_CGMR_CSS_MOSC (1<<14)
655 #define AT91_PMC_CGMR_CSS_PLL (2<<14)
656 #define AT91_PMC_CGMR_CSS_RES (3<<14)
658 #define AT91_PMC_CGMR_PLL_MUL(x) ((x)<<8)
659 #define AT91_PMC_CGMR_OSC_CNT(x) ((x)<<16)
660 #define AT91_PMC_CGMR_PLL_CNT(x) ((x)<<24)
662 #define AT91_PMC_PCR 0x28
663 #define AT91_PMC_PCR_SHDALC 1
664 #define AT91_PMC_PCR_WKACKC 2
666 #define AT91_PMC_PMR 0x2c
667 #define AT91_PMC_PMR_SHDALS_TRI 0
668 #define AT91_PMC_PMR_SHDALS_LEVEL0 1
669 #define AT91_PMC_PMR_SHDALS_LEVEL1 2
670 #define AT91_PMC_PMR_SHDALS_RES 3
671 #define AT91_PMC_PMR_WKACKS_TRI (0<<2)
672 #define AT91_PMC_PMR_WKACKS_LEVEL0 (1<<2)
673 #define AT91_PMC_PMR_WKACKS_LEVEL1 (2<<2)
674 #define AT91_PMC_PMR_WKACKS_RES (3<<2)
675 #define AT91_PMC_PMR_ALWKEN (1<<4)
676 #define AT91_PMC_PMR_ALSHEN (1<<5)
678 #define AT91_PMC_PMR_WKEDG_NONE (0<<6)
679 #define AT91_PMC_PMR_WKEDG_POS (1<<6)
680 #define AT91_PMC_PMR_WKEDG_NEG (2<<6)
681 #define AT91_PMC_PMR_WKEDG_BOTH (3<<6)
683 #define AT91_PMC_SR_MOSCS 0x01
684 #define AT91_PMC_SR_LOCK 0x02
688 #elif defined(CYGHWR_HAL_ARM_AT91_JTST)
689 // Now power management control for the JTST
692 #error Unknown AT91 variant
697 //=============================================================================
701 #define AT91_WD 0xFFFF8000
704 #define AT91_WD_OMR 0x00
705 #define AT91_WD_OMR_WDEN 0x00000001
706 #define AT91_WD_OMR_RSTEN 0x00000002
707 #define AT91_WD_OMR_IRQEN 0x00000004
708 #define AT91_WD_OMR_EXTEN 0x00000008
709 #define AT91_WD_OMR_OKEY (0x00000234 << 4)
710 #define AT91_WD_CMR 0x04
711 #define AT91_WD_CMR_WDCLKS 0x00000003
712 #define AT91_WD_CMR_HPCV 0x0000003C
713 #define AT91_WD_CMR_CKEY (0x0000006E << 7)
714 #define AT91_WD_CR 0x08
715 #define AT91_WD_CR_RSTKEY 0x0000C071
716 #define AT91_WD_SR 0x0C
717 #define AT91_WD_SR_WDOVF 0x00000001
719 //=============================================================================
723 #define AT91_SPI 0xFFFBC000
726 #define AT91_SPI_CR 0x00 // Control Register
727 #define AT91_SPI_CR_SPIEN 0x00000001 // SPI Enable
728 #define AT91_SPI_CR_SPIDIS 0x00000002 // SPI Disable
729 #define AT91_SPI_CR_SWRST 0x00000080 // SPI Software reset
730 #define AT91_SPI_MR 0x04 // Mode Register
731 #define AT91_SPI_MR_MSTR 0x00000001 // Master/Slave Mode
732 #define AT91_SPI_MR_PS 0x00000002 // Peripheral Select
733 #define AT91_SPI_MR_PCSDEC 0x00000004 // Chip Select Decode
734 #define AT91_SPI_MR_DIV32 0x00000008 // Clock Selection
735 #define AT91_SPI_MR_LLB 0x00000080 // Local Loopback Enable
736 #define AT91_SPI_MR_PCS(x) (((x)&0x0F)<<16) // Peripheral Chip Select
737 #define AT91_SPI_MR_DLYBCS(x) (((x)&0xFF)<<24) // Delay Between Chip Selects
738 #define AT91_SPI_RDR 0x08 // Receive Data Register
739 #define AT91_SPI_TDR 0x0C // Transmit Data Register
740 #define AT91_SPI_SR 0x10 // Status Register
741 #define AT91_SPI_SR_RDRF 0x00000001 // Receive Data Register Full
742 #define AT91_SPI_SR_TDRE 0x00000002 // Transmit Data Register Empty
743 #define AT91_SPI_SR_MODF 0x00000004 // Mode Fault Error
744 #define AT91_SPI_SR_OVRES 0x00000008 // Overrun Error Status
745 #define AT91_SPI_SR_ENDRX 0x00000010 // End of Receiver Transfer
746 #define AT91_SPI_SR_ENDTX 0x00000020 // End of Transmitter Transfer
747 #define AT91_SPI_SR_SPIENS 0x00010000 // SPI Enable Status
748 #define AT91_SPI_IER 0x14 // Interrupt Enable Register
749 #define AT91_SPI_IDR 0x18 // Interrupt Disable Register
750 #define AT91_SPI_IMR 0x1C // Interrupt Mask Register
751 // DMA registers are PDC registers
752 // can be different from target to target
754 #define AT91_SPI_RPR 0x20 // Receive Pointer Register
757 #define AT91_SPI_RCR 0x24 // Receive Counter Register
760 #define AT91_SPI_TPR 0x28 // Transmit Pointer Register
763 #define AT91_SPI_TCR 0x2C // Transmit Counter Register
765 #define AT91_SPI_CSR0 0x30 // Chip Select Register 0
766 #define AT91_SPI_CSR1 0x34 // Chip Select Register 1
767 #define AT91_SPI_CSR2 0x38 // Chip Select Register 2
768 #define AT91_SPI_CSR3 0x3C // Chip Select Register 3
769 #define AT91_SPI_CSR_CPOL 0x00000001 // Clock Polarity
770 #define AT91_SPI_CSR_NCPHA 0x00000002 // Clock Phase
771 #define AT91_SPI_CSR_BITS(x) (((x)&0x0F)<<4) // Bits Per Transfer
772 #define AT91_SPI_CSR_BITS8 AT91_SPI_CSR_BITS(0)
773 #define AT91_SPI_CSR_BITS9 AT91_SPI_CSR_BITS(1)
774 #define AT91_SPI_CSR_BITS10 AT91_SPI_CSR_BITS(2)
775 #define AT91_SPI_CSR_BITS11 AT91_SPI_CSR_BITS(3)
776 #define AT91_SPI_CSR_BITS12 AT91_SPI_CSR_BITS(4)
777 #define AT91_SPI_CSR_BITS13 AT91_SPI_CSR_BITS(5)
778 #define AT91_SPI_CSR_BITS14 AT91_SPI_CSR_BITS(6)
779 #define AT91_SPI_CSR_BITS15 AT91_SPI_CSR_BITS(7)
780 #define AT91_SPI_CSR_BITS16 AT91_SPI_CSR_BITS(8)
781 #define AT91_SPI_CSR_SCBR(x) (((x)&0xFF)<<8) // Serial Clock Baud Rate
782 #define AT91_SPI_CSR_DLYBS(x) (((x)&0xFF)<<16) // Delay Before SPCK
783 #define AT91_SPI_CSR_DLYBCT(x) (((x)&0xFF)<<24) // Delay Between two transfers
785 #if defined(CYGHWR_HAL_ARM_AT91_M55800A)
787 #define AT91_SPI_PIO AT91_PIOA
788 #define AT91_SPI_PIO_NPCS(x) (((x)&0x0F)<<26)
791 //=============================================================================
792 // FIQ interrupt vector which is shared by all HAL varients.
794 #define CYGNUM_HAL_INTERRUPT_FIQ 0
795 //-----------------------------------------------------------------------------
797 #endif // CYGONCE_HAL_VAR_IO_H
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