packages/hal/mips/arch/v2_0/include/hal_arch.h

   1 #ifndef CYGONCE_HAL_HAL_ARCH_H
   2 #define CYGONCE_HAL_HAL_ARCH_H
   3
   4 //==========================================================================
   5 //
   6 //      hal_arch.h
   7 //
   8 //      Architecture specific abstractions
   9 //
  10 //==========================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //==========================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):    nickg
  47 // Contributors: nickg, dmoseley
  48 // Date:         1999-02-17
  49 // Purpose:      Define architecture abstractions
  50 // Usage:        #include <cyg/hal/hal_arch.h>
  51 //
  52 //####DESCRIPTIONEND####
  53 //
  54 //==========================================================================
  55
  56 #ifndef __ASSEMBLER__
  57 #include <pkgconf/hal.h>
  58 #include <cyg/infra/cyg_type.h>
  59
  60 #include <cyg/hal/var_arch.h>
  61
  62 //--------------------------------------------------------------------------
  63 // Processor saved states:
  64 // The layout of this structure is also defined in "arch.inc", for assembly
  65 // code. Do not change this without changing that (or vice versa).
  66 // Notes: This structure is carefully laid out. It is a multiple of 8
  67 // bytes and the pc and badvr fields are positioned to ensure that
  68 // they are on 8 byte boundaries.
  69
  70 #ifdef CYGHWR_HAL_MIPS_64BIT
  71 # define CYG_HAL_MIPS_REG CYG_WORD64
  72 # define CYG_HAL_MIPS_REG_SIZE 8
  73 #else
  74 # define CYG_HAL_MIPS_REG CYG_WORD32
  75 # define CYG_HAL_MIPS_REG_SIZE 4
  76 #endif
  77
  78 #if defined(CYGHWR_HAL_MIPS_FPU)
  79 # if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
  80 #  define CYG_HAL_FPU_REG CYG_WORD64
  81 # elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
  82 #  define CYG_HAL_FPU_REG CYG_WORD32
  83 # else
  84 # error MIPS FPU register size not defined
  85 # endif
  86 #endif
  87
  88 typedef struct
  89 {
  90     // These are common to all saved states
  91     CYG_HAL_MIPS_REG    d[32];          /* Data regs                    */
  92     CYG_HAL_MIPS_REG    hi;             /* hi word of mpy/div reg       */
  93     CYG_HAL_MIPS_REG    lo;             /* lo word of mpy/div reg       */
  94 #ifdef CYGHWR_HAL_MIPS_FPU
  95     CYG_HAL_FPU_REG     f[32];          /* FPU registers                */
  96     CYG_WORD32          fcr31;          /* FPU control/status register  */
  97     CYG_WORD32          fppad;          /* Dummy location to make this  */
  98                                         /* structure a multiple of 8    */
  99                                         /* bytes long.                  */
 100 #endif
 101
 102     // These are only saved for exceptions and interrupts
 103     CYG_WORD32          vector;         /* Vector number                */
 104     CYG_WORD32          sr;             /* Status Reg                   */
 105     CYG_HAL_MIPS_REG    pc;             /* Program Counter              */
 106     CYG_WORD32          cache;          /* Cache control register       */
 107
 108
 109     // These are only saved for exceptions, and are not restored
 110     // when continued.
 111     CYG_WORD32          cause;          /* Exception cause register     */
 112     CYG_HAL_MIPS_REG    badvr;          /* Bad virtual address reg      */
 113     CYG_WORD32          prid;           /* Processor Version            */
 114     CYG_WORD32          config;         /* Config register              */
 115 } HAL_SavedRegisters;
 116
 117 //--------------------------------------------------------------------------
 118 // Exception handling function.
 119 // This function is defined by the kernel according to this prototype. It is
 120 // invoked from the HAL to deal with any CPU exceptions that the HAL does
 121 // not want to deal with itself. It usually invokes the kernel's exception
 122 // delivery mechanism.
 123
 124 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
 125
 126 //--------------------------------------------------------------------------
 127 // Bit manipulation macros
 128
 129 externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
 130 externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
 131
 132 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
 133
 134 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
 135
 136 //--------------------------------------------------------------------------
 137 // Context Initialization
 138
 139
 140 // Optional FPU context initialization
 141 #ifdef CYGHWR_HAL_MIPS_FPU
 142 #define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ )                             \
 143 {                                                                               \
 144     for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->f[_i_] = (_id_)|0xFF00|_i_;       \
 145     (_regs_)->fcr31 = 0x01000000;                                               \
 146 }
 147 #else
 148 #define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ )
 149 #endif
 150
 151
 152 // Initialize the context of a thread.
 153 // Arguments:
 154 // _sparg_ name of variable containing current sp, will be written with new sp
 155 // _thread_ thread object address, passed as argument to entry point
 156 // _entry_ entry point address.
 157 // _id_ bit pattern used in initializing registers, for debugging.
 158 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )                     \
 159 {                                                                                       \
 160     register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-56;                                    \
 161     register HAL_SavedRegisters *_regs_;                                                \
 162     int _i_;                                                                            \
 163     _sp_ = _sp_ & 0xFFFFFFF0;                                                           \
 164     _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters))&0xFFFFFFF0);  \
 165     for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_;                      \
 166     HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ );                                        \
 167     (_regs_)->d[29] = (CYG_HAL_MIPS_REG)(_sp_);       /* SP = top of stack      */      \
 168     (_regs_)->d[04] = (CYG_HAL_MIPS_REG)(_thread_);   /* R4 = arg1 = thread ptr */      \
 169     (_regs_)->lo = 0;                                 /* LO = 0                 */      \
 170     (_regs_)->hi = 0;                                 /* HI = 0                 */      \
 171     (_regs_)->d[30] = (CYG_HAL_MIPS_REG)(_sp_);       /* FP = top of stack      */      \
 172     (_regs_)->d[31] = (CYG_HAL_MIPS_REG)(_entry_);    /* RA(d[31]) = entry point*/      \
 173     (_regs_)->pc = (CYG_WORD)(_entry_);               /* PC = entry point       */      \
 174     (_regs_)->sr  = 0x00000001;                       /* SR = ls 3 bits only    */      \
 175     _sparg_ = (CYG_ADDRESS)_regs_;                                                      \
 176 }
 177
 178 //--------------------------------------------------------------------------
 179 // Context switch macros.
 180 // The arguments are pointers to locations where the stack pointer
 181 // of the current thread is to be stored, and from where the sp of the
 182 // next thread is to be fetched.
 183
 184 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
 185 externC void hal_thread_load_context( CYG_ADDRESS to )
 186     __attribute__ ((noreturn));
 187
 188 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_)                    \
 189         hal_thread_switch_context( (CYG_ADDRESS)_tspptr_,               \
 190                                    (CYG_ADDRESS)_fspptr_);
 191
 192 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_)                               \
 193         hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
 194
 195 //--------------------------------------------------------------------------
 196 // Execution reorder barrier.
 197 // When optimizing the compiler can reorder code. In multithreaded systems
 198 // where the order of actions is vital, this can sometimes cause problems.
 199 // This macro may be inserted into places where reordering should not happen.
 200 // The "memory" keyword is potentially unnecessary, but it is harmless to
 201 // keep it.
 202
 203 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
 204
 205 //--------------------------------------------------------------------------
 206 // Breakpoint support
 207 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
 208 // happen if executed.
 209 // HAL_BREAKINST is the value of the breakpoint instruction and
 210 // HAL_BREAKINST_SIZE is its size in bytes.
 211 // HAL_BREAKINST_TYPE is the type.
 212
 213 #define HAL_BREAKPOINT(_label_)                 \
 214 asm volatile (" .globl  " #_label_ ";"          \
 215               #_label_":"                       \
 216               " break   5"                      \
 217     );
 218
 219 #define HAL_BREAKINST           0x0005000d
 220
 221 #define HAL_BREAKINST_SIZE      4
 222
 223 #define HAL_BREAKINST_TYPE      cyg_uint32
 224
 225 //--------------------------------------------------------------------------
 226 // Thread register state manipulation for GDB support.
 227
 228 // Default to a 32 bit register size for GDB register dumps.
 229 #ifndef CYG_HAL_GDB_REG
 230 #define CYG_HAL_GDB_REG CYG_WORD32
 231 #endif
 232
 233 // Translate a stack pointer as saved by the thread context macros above into
 234 // a pointer to a HAL_SavedRegisters structure.
 235 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ )          \
 236         (_regs_) = (HAL_SavedRegisters *)(_sp_)
 237
 238 // If the CPU has an FPU, we also need to move the FPU registers.
 239 #ifdef CYGHWR_HAL_MIPS_FPU
 240 #define HAL_GET_GDB_FPU_REGISTERS( _regval_ , _regs_ )  \
 241 CYG_MACRO_START                                         \
 242     int _i_;                                            \
 243     for( _i_ = 0; _i_ < 32; _i_++ )                     \
 244         _regval_[38+_i_] = (_regs_)->f[_i_];            \
 245     _regval_[70] = (_regs_)->fcr31;                     \
 246 CYG_MACRO_END
 247 #define HAL_SET_GDB_FPU_REGISTERS( _regs_ , _regval_ )  \
 248 CYG_MACRO_START                                         \
 249     int _i_;                                            \
 250     for( _i_ = 0; _i_ < 32; _i_++ )                     \
 251         (_regs_)->f[_i_] = _regval_[38+_i_];            \
 252     (_regs_)->fcr31 = _regval_[70];                     \
 253 CYG_MACRO_END
 254 #else
 255 #define HAL_GET_GDB_FPU_REGISTERS( _regval_ , _regs_ )
 256 #define HAL_SET_GDB_FPU_REGISTERS( _regs_ , _regval_ )
 257 #endif
 258
 259 // Some targets also report the state of all the coprocessor 0
 260 // registers to GDB. If that is the case then
 261 // CYGPKG_HAL_MIPS_GDB_REPORT_CP0 will be defined and the
 262 // HAL_[G|S]ET_CP0_REGISTER_*() macros will be defined.
 263
 264 #ifdef CYGPKG_HAL_MIPS_GDB_REPORT_CP0
 265
 266 #define HAL_GET_GDB_CP0_REGISTERS( _regval_, _regs_ )                   \
 267     HAL_GET_CP0_REGISTER_32( _regval_[74],   0, 0 ); /* index    */     \
 268     HAL_GET_CP0_REGISTER_32( _regval_[75],   1, 0 ); /* random   */     \
 269     HAL_GET_CP0_REGISTER_32( _regval_[76],   2, 0 ); /* EntryLo0 */     \
 270     HAL_GET_CP0_REGISTER_32( _regval_[77],   3, 0 ); /* EntryLo1 */     \
 271     HAL_GET_CP0_REGISTER_64( _regval_[78],   4, 0 ); /* context  */     \
 272     HAL_GET_CP0_REGISTER_32( _regval_[79],   5, 0 ); /* PageMask */     \
 273     HAL_GET_CP0_REGISTER_32( _regval_[80],   6, 0 ); /* Wired    */     \
 274     (_regval_)[81] = 0xC0C0C006;                                        \
 275     (_regval_)[82] = (_regs_)->badvr;                /* BadVr    */     \
 276     HAL_GET_CP0_REGISTER_32( _regval_[83],   9, 0 ); /* Count    */     \
 277     HAL_GET_CP0_REGISTER_64( _regval_[84],  10, 0 ); /* EntryHi  */     \
 278     HAL_GET_CP0_REGISTER_32( _regval_[85],  11, 0 ); /* Compare  */     \
 279     (_regval_)[86] = (_regs_)->sr;                   /* Status   */     \
 280     (_regval_)[87] = (_regs_)->cause;                /* Cause    */     \
 281     HAL_GET_CP0_REGISTER_64( _regval_[88],  14, 0 ); /* EPC      */     \
 282     HAL_GET_CP0_REGISTER_32( _regval_[89],  15, 0 ); /* PRId     */     \
 283     HAL_GET_CP0_REGISTER_32( _regval_[90],  16, 0 ); /* Config   */     \
 284     HAL_GET_CP0_REGISTER_32( _regval_[91],  17, 0 ); /* LLAddr   */     \
 285     HAL_GET_CP0_REGISTER_64( _regval_[92],  18, 0 ); /* WatchLo  */     \
 286     HAL_GET_CP0_REGISTER_32( _regval_[93],  19, 0 ); /* WatchHi  */     \
 287     HAL_GET_CP0_REGISTER_64( _regval_[94],  20, 0 ); /* XContext */     \
 288     (_regval_)[95] = 0xC0C0C021;                                        \
 289     (_regval_)[96] = 0xC0C0C022;                                        \
 290     HAL_GET_CP0_REGISTER_32( _regval_[97],  23, 0 ); /* Debug    */     \
 291     HAL_GET_CP0_REGISTER_64( _regval_[98],  24, 0 ); /* DEPC     */     \
 292     (_regval_)[99] = 0xC0C0C025;                                        \
 293     HAL_GET_CP0_REGISTER_32( _regval_[100], 26, 0 ); /* ErrCtl   */     \
 294     HAL_GET_CP0_REGISTER_32( _regval_[101], 27, 0 ); /* CacheErr */     \
 295     HAL_GET_CP0_REGISTER_32( _regval_[102], 28, 0 ); /* TagLo    */     \
 296     HAL_GET_CP0_REGISTER_32( _regval_[103], 29, 0 ); /* TagHi    */     \
 297     HAL_GET_CP0_REGISTER_64( _regval_[104], 30, 0 ); /* ErrorEPC */     \
 298     HAL_GET_CP0_REGISTER_64( _regval_[105], 31, 0 ); /* DESAVE   */     \
 299     HAL_GET_CP0_REGISTER_32( _regval_[106], 16, 1 ); /* Config1  */
 300
 301 #define HAL_SET_GDB_CP0_REGISTERS( _regval_, _regs_ )                   \
 302     HAL_SET_CP0_REGISTER_32( _regval_[74],   0, 0 ); /* index    */     \
 303     HAL_SET_CP0_REGISTER_32( _regval_[76],   2, 0 ); /* EntryLo0 */     \
 304     HAL_SET_CP0_REGISTER_32( _regval_[77],   3, 0 ); /* EntryLo1 */     \
 305     HAL_SET_CP0_REGISTER_64( _regval_[78],   4, 0 ); /* context  */     \
 306     HAL_SET_CP0_REGISTER_32( _regval_[79],   5, 0 ); /* PageMask */     \
 307     HAL_SET_CP0_REGISTER_32( _regval_[80],   6, 0 ); /* Wired    */     \
 308     HAL_SET_CP0_REGISTER_32( _regval_[83],   9, 0 ); /* Count    */     \
 309     HAL_SET_CP0_REGISTER_64( _regval_[84],  10, 0 ); /* EntryHi  */     \
 310     HAL_SET_CP0_REGISTER_32( _regval_[85],  11, 0 ); /* Compare  */     \
 311     HAL_SET_CP0_REGISTER_32( _regval_[90],  16, 0 ); /* Config   */     \
 312     HAL_SET_CP0_REGISTER_64( _regval_[92],  18, 0 ); /* WatchLo  */     \
 313     HAL_SET_CP0_REGISTER_32( _regval_[93],  19, 0 ); /* WatchHi  */     \
 314     HAL_SET_CP0_REGISTER_64( _regval_[94],  20, 0 ); /* XContext */     \
 315     HAL_SET_CP0_REGISTER_32( _regval_[97],  23, 0 ); /* Debug    */     \
 316     HAL_SET_CP0_REGISTER_64( _regval_[98],  24, 0 ); /* DEPC     */     \
 317     HAL_SET_CP0_REGISTER_32( _regval_[100], 26, 0 ); /* ErrCtl   */     \
 318     HAL_SET_CP0_REGISTER_32( _regval_[101], 27, 0 ); /* CacheErr */     \
 319     HAL_SET_CP0_REGISTER_32( _regval_[102], 28, 0 ); /* TagLo    */     \
 320     HAL_SET_CP0_REGISTER_32( _regval_[103], 29, 0 ); /* TagHi    */     \
 321     HAL_SET_CP0_REGISTER_64( _regval_[105], 31, 0 ); /* DESAVE   */
 322
 323 #else
 324 #define HAL_GET_GDB_CP0_REGISTERS( _regval_, _regs_ )
 325 #define HAL_SET_GDB_CP0_REGISTERS( _regval_, _regs_ )
 326 #endif
 327
 328 // Copy a set of registers from a HAL_SavedRegisters structure into a
 329 // GDB ordered array.
 330 #define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ )             \
 331 {                                                               \
 332     CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
 333     int _i_;                                                    \
 334                                                                 \
 335     for( _i_ = 0; _i_ < 32; _i_++ )                             \
 336         _regval_[_i_] = (_regs_)->d[_i_];                       \
 337                                                                 \
 338     HAL_GET_GDB_FPU_REGISTERS( _regval_, _regs_ );              \
 339                                                                 \
 340     _regval_[32] = (_regs_)->sr;                                \
 341     _regval_[33] = (_regs_)->lo;                                \
 342     _regval_[34] = (_regs_)->hi;                                \
 343     _regval_[35] = (_regs_)->badvr;                             \
 344     _regval_[36] = (_regs_)->cause;                             \
 345     _regval_[37] = (_regs_)->pc;                                \
 346                                                                 \
 347     HAL_GET_GDB_CP0_REGISTERS( _regval_, _regs_ );              \
 348 }
 349
 350 // Copy a GDB ordered array into a HAL_SavedRegisters structure.
 351 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ )             \
 352 {                                                               \
 353     CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
 354     int _i_;                                                    \
 355                                                                 \
 356     for( _i_ = 0; _i_ < 32; _i_++ )                             \
 357         (_regs_)->d[_i_] = _regval_[_i_];                       \
 358                                                                 \
 359     HAL_SET_GDB_FPU_REGISTERS( _regs_, _regval_ );              \
 360                                                                 \
 361     (_regs_)->sr = _regval_[32];                                \
 362     (_regs_)->lo = _regval_[33];                                \
 363     (_regs_)->hi = _regval_[34];                                \
 364     (_regs_)->badvr = _regval_[35];                             \
 365     (_regs_)->cause = _regval_[36];                             \
 366     (_regs_)->pc = _regval_[37];                                \
 367                                                                 \
 368     HAL_SET_GDB_CP0_REGISTERS( _regval_, _regs_ );              \
 369 }
 370
 371 //--------------------------------------------------------------------------
 372 // HAL setjmp
 373 // Note: These definitions are repeated in hal_arch.h. If changes are
 374 // required remember to update both sets.
 375
 376 #define CYGARC_JMP_BUF_SP        0
 377 #define CYGARC_JMP_BUF_R16       1
 378 #define CYGARC_JMP_BUF_R17       2
 379 #define CYGARC_JMP_BUF_R18       3
 380 #define CYGARC_JMP_BUF_R19       4
 381 #define CYGARC_JMP_BUF_R20       5
 382 #define CYGARC_JMP_BUF_R21       6
 383 #define CYGARC_JMP_BUF_R22       7
 384 #define CYGARC_JMP_BUF_R23       8
 385 #define CYGARC_JMP_BUF_R28       9
 386 #define CYGARC_JMP_BUF_R30      10
 387 #define CYGARC_JMP_BUF_R31      11
 388
 389 #define CYGARC_JMP_BUF_SIZE     12
 390
 391 typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
 392
 393 externC int hal_setjmp(hal_jmp_buf env);
 394 externC void hal_longjmp(hal_jmp_buf env, int val);
 395
 396 //-------------------------------------------------------------------------
 397 // Idle thread code.
 398 // This macro is called in the idle thread loop, and gives the HAL the
 399 // chance to insert code. Typical idle thread behaviour might be to halt the
 400 // processor.
 401
 402 externC void hal_idle_thread_action(cyg_uint32 loop_count);
 403
 404 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
 405
 406 //--------------------------------------------------------------------------
 407 // Minimal and sensible stack sizes: the intention is that applications
 408 // will use these to provide a stack size in the first instance prior to
 409 // proper analysis.  Idle thread stack should be this big.
 410
 411 //    THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
 412 //           THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
 413 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
 414
 415 // This is not a config option because it should not be adjusted except
 416 // under "enough rope" sort of disclaimers.
 417
 418 // Typical case stack frame size: return link + 4 pushed registers + some locals.
 419 #define CYGNUM_HAL_STACK_FRAME_SIZE (48)
 420
 421 // Stack needed for a context switch:
 422 #if defined(CYGHWR_HAL_MIPS_FPU)
 423 # if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
 424 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*CYG_HAL_MIPS_REG_SIZE)+(32*8))
 425 # elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
 426 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*CYG_HAL_MIPS_REG_SIZE)+(32*4))
 427 # else
 428 # error MIPS FPU register size not defined
 429 # endif
 430 #else
 431 #define CYGNUM_HAL_STACK_CONTEXT_SIZE ((32+10)*CYG_HAL_MIPS_REG_SIZE)
 432 #endif
 433
 434
 435
 436 // Interrupt + call to ISR, interrupt_end() and the DSR
 437 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE)
 438
 439 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 440
 441 // An interrupt stack which is large enough for all possible interrupt
 442 // conditions (and only used for that purpose) exists.  "User" stacks
 443 // can be much smaller
 444
 445 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+      \
 446                                        CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+  \
 447                                        CYGNUM_HAL_STACK_FRAME_SIZE*8)
 448 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (CYGNUM_HAL_STACK_SIZE_MINIMUM+1024)
 449
 450 #else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 451
 452 // No separate interrupt stack exists.  Make sure all threads contain
 453 // a stack sufficiently large.
 454
 455 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096)
 456 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096)
 457
 458 #endif
 459
 460 #endif /* __ASSEMBLER__ */
 461
 462 // Convenience macros for accessing memory cached or uncached
 463 #define CYGARC_KSEG_MASK                               (0xE0000000)
 464 #define CYGARC_KSEG_CACHED                             (0x80000000)
 465 #define CYGARC_KSEG_UNCACHED                           (0xA0000000)
 466 #define CYGARC_KSEG_CACHED_BASE                        (0x80000000)
 467 #define CYGARC_KSEG_UNCACHED_BASE                      (0xA0000000)
 468 #ifndef __ASSEMBLER__
 469 #define CYGARC_CACHED_ADDRESS(x)                       ((((CYG_ADDRESS)(x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_CACHED)
 470 #define CYGARC_UNCACHED_ADDRESS(x)                     ((((CYG_ADDRESS)(x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_UNCACHED)
 471 #define CYGARC_PHYSICAL_ADDRESS(x)                     (((CYG_ADDRESS)(x)) & ~CYGARC_KSEG_MASK)
 472 #else // __ASSEMBLER__
 473 #define CYGARC_CACHED_ADDRESS(x)                       ((((x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_CACHED)
 474 #define CYGARC_UNCACHED_ADDRESS(x)                     ((((x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_UNCACHED)
 475 #define CYGARC_PHYSICAL_ADDRESS(x)                     (((x)) & ~CYGARC_KSEG_MASK)
 476 #define CYGARC_ADDRESS_REG_CACHED(reg)                 \
 477         and     reg, reg, ~CYGARC_KSEG_MASK;           \
 478         or      reg, reg, CYGARC_KSEG_CACHED
 479 #define CYGARC_ADDRESS_REG_UNCACHED(reg)               \
 480         and     reg, reg, ~CYGARC_KSEG_MASK;           \
 481         or      reg, reg, CYGARC_KSEG_UNCACHED
 482 #endif /* __ASSEMBLER__ */
 483
 484 //--------------------------------------------------------------------------
 485 // Macros for switching context between two eCos instances (jump from
 486 // code in ROM to code in RAM or vice versa).
 487 #define CYGARC_HAL_SAVE_GP()                    \
 488     CYG_MACRO_START                             \
 489     register CYG_ADDRWORD __gp_save;            \
 490     asm volatile ( "move   %0,$28;"             \
 491                    ".extern _gp;"               \
 492                    "la     $gp,_gp;"            \
 493                      : "=r"(__gp_save))
 494
 495 #define CYGARC_HAL_RESTORE_GP()                                 \
 496     asm volatile ( "move   $gp,%0;" :: "r"(__gp_save) );        \
 497     CYG_MACRO_END
 498
 499
 500 //--------------------------------------------------------------------------
 501 // Macro for finding return address.
 502 #define CYGARC_HAL_GET_RETURN_ADDRESS(_x_, _dummy_) \
 503   asm volatile ( "move %0,$31;" : "=r" (_x_) )
 504
 505 #define CYGARC_HAL_GET_RETURN_ADDRESS_BACKUP(_dummy_)
 506
 507 //--------------------------------------------------------------------------
 508 #endif // CYGONCE_HAL_HAL_ARCH_H
 509 // End of hal_arch.h