1 //=============================================================================
5 // Platform specific code for GDB stub support.
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): dhowells
44 // Contributors:dmoseley
46 // Purpose: Platform specific code for GDB stub support.
48 //####DESCRIPTIONEND####
50 //=============================================================================
52 #include <pkgconf/hal.h>
53 #include <cyg/hal/hal_io.h> // HAL IO macros
55 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
57 #include <cyg/hal/hal_stub.h>
58 #include <cyg/hal/hal_intr.h> // HAL interrupt macros
60 /*---------------------------------------------------------------------------*/
61 // Define the serial registers.
62 #define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0
63 #define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0
64 #define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
65 #define CYG_DEV_IER 0x04 // interrupt enable register, read/write, dlab = 0
66 #define CYG_DEV_DLM 0x04 // divisor latch (MS), read/write, dlab = 1
67 #define CYG_DEV_IIR 0x08 // interrupt identification register, read, dlab = 0
68 #define CYG_DEV_FCR 0x08 // fifo control register, write, dlab = 0
69 #define CYG_DEV_LCR 0x0C // line control register, read/write
70 #define CYG_DEV_MCR 0x10 // modem control register, read/write
71 #define CYG_DEV_LSR 0x14 // line status register, read
72 #define CYG_DEV_MSR 0x18 // modem status register, read
74 // Interrupt Enable Register
75 #define SIO_IER_RCV 0x01
76 #define SIO_IER_XMT 0x02
77 #define SIO_IER_LS 0x04
78 #define SIO_IER_MS 0x08
80 // The line status register bits.
81 #define SIO_LSR_DR 0x01 // data ready
82 #define SIO_LSR_OE 0x02 // overrun error
83 #define SIO_LSR_PE 0x04 // parity error
84 #define SIO_LSR_FE 0x08 // framing error
85 #define SIO_LSR_BI 0x10 // break interrupt
86 #define SIO_LSR_THRE 0x20 // transmitter holding register empty
87 #define SIO_LSR_TEMT 0x40 // transmitter register empty
88 #define SIO_LSR_ERR 0x80 // any error condition
90 // The modem status register bits.
91 #define SIO_MSR_DCTS 0x01 // delta clear to send
92 #define SIO_MSR_DDSR 0x02 // delta data set ready
93 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator
94 #define SIO_MSR_DDCD 0x08 // delta data carrier detect
95 #define SIO_MSR_CTS 0x10 // clear to send
96 #define SIO_MSR_DSR 0x20 // data set ready
97 #define SIO_MSR_RI 0x40 // ring indicator
98 #define SIO_MSR_DCD 0x80 // data carrier detect
100 // The line control register bits.
101 #define SIO_LCR_WLS0 0x01 // word length select bit 0
102 #define SIO_LCR_WLS1 0x02 // word length select bit 1
103 #define SIO_LCR_STB 0x04 // number of stop bits
104 #define SIO_LCR_PEN 0x08 // parity enable
105 #define SIO_LCR_EPS 0x10 // even parity select
106 #define SIO_LCR_SP 0x20 // stick parity
107 #define SIO_LCR_SB 0x40 // set break
108 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
110 // Modem Control Register
111 #define SIO_MCR_DTR 0x01
112 #define SIO_MCR_RTS 0x02
113 #define SIO_MCR_INT 0x08 // Enable interrupts
115 #define SERIAL0BASE 0x86FB0000
117 //---------------------------------------------------------------------------
119 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
120 // This ISR is called from the interrupt handler. This should only
121 // happen when there is no serial driver, so the code shouldn't mess
123 int cyg_hal_gdb_isr(cyg_uint32 vector, target_register_t pc)
125 if ( CYGNUM_HAL_INTERRUPT_SERIAL_0_RX == vector ) {
128 HAL_READ_UINT8(SERIAL0BASE+CYG_DEV_RBR,c);
129 HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SERIAL_0_RX);
133 // Ctrl-C: set a breakpoint at PC so GDB will display the
134 // correct program context when stopping rather than the
135 // interrupt handler.
136 cyg_hal_gdb_interrupt (pc);
138 // Interrupt handled. Don't call ISR proper. At return
139 // from the VSR, execution will stop at the breakpoint
145 // Not caused by GDB. Call ISR proper.
150 //-----------------------------------------------------------------------------
152 void hal_asb_platform_init(void)
154 extern CYG_ADDRESS hal_virtual_vector_table[64];
155 extern void init_thread_syscall( void *);
156 extern void install_async_breakpoint(void *epc);
157 // void (*oldvsr)(void);
158 extern void _default_trap_vsr(void);
160 // Ensure that the breakpoint VSR points to the default VSR. This will pass
161 // it on to the stubs.
162 // HAL_VSR_SET( CYGNUM_HAL_VECTOR_BREAKPOINT, _default_trap_vsr, &oldvsr );
164 // Install async breakpoint handler into vector table.
165 hal_virtual_vector_table[35] = (CYG_ADDRESS)install_async_breakpoint;
167 #if !defined(CYGPKG_KERNEL) && defined(CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT)
168 // Only include this code if we do not have a kernel. Otherwise
169 // the kernel supplies the functionality for the app we are linked
172 // Prepare for application installation of thread info function in
174 hal_virtual_vector_table[15] = 0;
175 init_thread_syscall( (void *)&hal_virtual_vector_table[15] );
179 #endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
181 /*------------------------------------------------------------------------*/
184 #define RSTCTR 0xc0001004
186 void cyg_hal_plf_reset(void)
188 // Unfortunately this only resets the MN103E010
189 // A full board reset is not done. ie If the boot block select switched,
190 // and a Cygmon reset called the switch change will not occur. AFAICT
191 // the only way to notice that change is to use the Reset switch on the
193 HAL_WRITE_UINT8(RSTCTR, 0x00);
194 HAL_WRITE_UINT8(RSTCTR, CHIPRST);
201 //-----------------------------------------------------------------------------