#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
#define PWDT 1 /* 0: disabled 1: precharge pwdn
2: pwdn after 64 clocks 3: pwdn after 128 clocks */
-#define FP 1 /* 0: not full page 1: full page */
+#define FP 0 /* 0: not full page 1: full page */
#define BL 1 /* 0: 4(not for LPDDR) 1: 8 */
#define PRCT 0 /* 0: disabled *: clks / 2 (0..63) */
#define ESDCTLVAL (0x80000000 | (RA_BITS << 24) | (CA_BITS << 20) | \
#define tWR 0 /* clks - 2 (0..1) */ // 0
#define tRAS 5 /* clks - 1 (0..7) */ // 5
#define tRRD 1 /* clks - 1 (0..3) */ // 1
-#define tCAS 2 /* 0: 3 clks[LPDDR] 1: rsrvd *: clks (2..3) */ // 3
+#define tCAS 3 /* 0: 3 clks[LPDDR] 1: rsrvd *: clks (2..3) */ // 3
#define tRCD 2 /* clks - 1 (0..7) */ // 2
-#define tRC 7 /* 0: 20 *: clks - 1 (0..15) */ // 8
+#define tRC 8 /* 0: 20 *: clks - 1 (0..15) */ // 8
#define ESDCFGVAL ((tXP << 21) | (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
(tWR << 15) | (tRAS << 12) | (tRRD << 10) | (tCAS << 8) | \