arch/arm/cpu/armv7/am33xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Common board functions for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <asm/arch/cpu.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/arch/omap.h>
  24 #include <asm/arch/ddr_defs.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/mmc_host_def.h>
  28 #include <asm/arch/common_def.h>
  29 #include <asm/io.h>
  30 #include <asm/omap_common.h>
  31 #include <asm/emif.h>
  32 #include <asm/gpio.h>
  33 #include <i2c.h>
  34 #include <miiphy.h>
  35 #include <cpsw.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  40 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
  41 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  42
  43 static const struct gpio_bank gpio_bank_am33xx[4] = {
  44         { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
  45         { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
  46         { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
  47         { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
  48 };
  49
  50 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
  51
  52 /* MII mode defines */
  53 #define MII_MODE_ENABLE         0x0
  54 #define RGMII_MODE_ENABLE       0xA
  55
  56 /* GPIO that controls power to DDR on EVM-SK */
  57 #define GPIO_DDR_VTT_EN         7
  58
  59 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  60
  61 /*
  62  * I2C Address of on-board EEPROM
  63  */
  64 #define I2C_BASE_BOARD_ADDR     0x50
  65
  66 #define NO_OF_MAC_ADDR          3
  67 #define ETH_ALEN                6
  68 #define NAME_LEN                8
  69
  70 struct am335x_baseboard_id {
  71         unsigned int  magic;
  72         char name[NAME_LEN];
  73         char version[4];
  74         char serial[12];
  75         char config[32];
  76         char mac_addr[NO_OF_MAC_ADDR][ETH_ALEN];
  77 };
  78
  79 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
  80
  81 static inline int board_is_bone(void)
  82 {
  83         return !strncmp(header.name, "A335BONE", NAME_LEN);
  84 }
  85
  86 static inline int board_is_evm_sk(void)
  87 {
  88         return !strncmp("A335X_SK", header.name, NAME_LEN);
  89 }
  90
  91 /*
  92  * Read header information from EEPROM into global structure.
  93  */
  94 static int read_eeprom(void)
  95 {
  96         /* Check if baseboard eeprom is available */
  97         if (i2c_probe(I2C_BASE_BOARD_ADDR)) {
  98                 puts("Could not probe the EEPROM; something fundamentally "
  99                         "wrong on the I2C bus.\n");
 100                 return -ENODEV;
 101         }
 102
 103         /* read the eeprom using i2c */
 104         if (i2c_read(I2C_BASE_BOARD_ADDR, 0, 2, (uchar *)&header,
 105                                                         sizeof(header))) {
 106                 puts("Could not read the EEPROM; something fundamentally"
 107                         " wrong on the I2C bus.\n");
 108                 return -EIO;
 109         }
 110
 111         if (header.magic != 0xEE3355AA) {
 112                 /*
 113                  * read the eeprom using i2c again,
 114                  * but use only a 1 byte address
 115                  */
 116                 if (i2c_read(I2C_BASE_BOARD_ADDR, 0, 1, (uchar *)&header,
 117                                                         sizeof(header))) {
 118                         puts("Could not read the EEPROM; something "
 119                                 "fundamentally wrong on the I2C bus.\n");
 120                         return -EIO;
 121                 }
 122
 123                 if (header.magic != 0xEE3355AA) {
 124                         printf("Incorrect magic number (0x%x) in EEPROM\n",
 125                                         header.magic);
 126                         return -EINVAL;
 127                 }
 128         }
 129
 130         return 0;
 131 }
 132
 133 /* UART Defines */
 134 #ifdef CONFIG_SPL_BUILD
 135 #define UART_RESET              (0x1 << 1)
 136 #define UART_CLK_RUNNING_MASK   0x1
 137 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
 138 #endif
 139
 140 #ifdef CONFIG_SPL_BUILD
 141 /* Initialize timer */
 142 static void init_timer(void)
 143 {
 144         /* Reset the Timer */
 145         writel(0x2, (&timer_base->tscir));
 146
 147         /* Wait until the reset is done */
 148         while (readl(&timer_base->tiocp_cfg) & 1)
 149                 ;
 150
 151         /* Start the Timer */
 152         writel(0x1, (&timer_base->tclr));
 153 }
 154 #endif
 155
 156 /*
 157  * Determine what type of DDR we have.
 158  */
 159 static short inline board_memory_type(void)
 160 {
 161         /* The following boards are known to use DDR3. */
 162         if (board_is_evm_sk())
 163                 return EMIF_REG_SDRAM_TYPE_DDR3;
 164
 165         return EMIF_REG_SDRAM_TYPE_DDR2;
 166 }
 167
 168 /*
 169  * early system init of muxing and clocks.
 170  */
 171 void s_init(void)
 172 {
 173         /* WDT1 is already running when the bootloader gets control
 174          * Disable it to avoid "random" resets
 175          */
 176         writel(0xAAAA, &wdtimer->wdtwspr);
 177         while (readl(&wdtimer->wdtwwps) != 0x0)
 178                 ;
 179         writel(0x5555, &wdtimer->wdtwspr);
 180         while (readl(&wdtimer->wdtwwps) != 0x0)
 181                 ;
 182
 183 #ifdef CONFIG_SPL_BUILD
 184         /* Setup the PLLs and the clocks for the peripherals */
 185         pll_init();
 186
 187         /* UART softreset */
 188         u32 regVal;
 189
 190         enable_uart0_pin_mux();
 191
 192         regVal = readl(&uart_base->uartsyscfg);
 193         regVal |= UART_RESET;
 194         writel(regVal, &uart_base->uartsyscfg);
 195         while ((readl(&uart_base->uartsyssts) &
 196                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 197                 ;
 198
 199         /* Disable smart idle */
 200         regVal = readl(&uart_base->uartsyscfg);
 201         regVal |= UART_SMART_IDLE_EN;
 202         writel(regVal, &uart_base->uartsyscfg);
 203
 204         /* Initialize the Timer */
 205         init_timer();
 206
 207         preloader_console_init();
 208
 209         /* Initalize the board header */
 210         enable_i2c0_pin_mux();
 211         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 212         if (read_eeprom() < 0)
 213                 puts("Could not get board ID.\n");
 214
 215         if (board_is_evm_sk()) {
 216                 /*
 217                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 218                  * This is safe enough to do on older revs.
 219                  */
 220                 enable_gpio0_7_pin_mux();
 221                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 222                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 223         }
 224
 225         config_ddr(board_memory_type());
 226 #endif
 227
 228         /* Enable MMC0 */
 229         enable_mmc0_pin_mux();
 230 }
 231
 232 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 233 int board_mmc_init(bd_t *bis)
 234 {
 235         return omap_mmc_init(0, 0, 0);
 236 }
 237 #endif
 238
 239 void setup_clocks_for_console(void)
 240 {
 241         /* Not yet implemented */
 242         return;
 243 }
 244
 245 /*
 246  * Basic board specific setup
 247  */
 248 int board_init(void)
 249 {
 250         enable_uart0_pin_mux();
 251
 252         enable_i2c0_pin_mux();
 253         enable_i2c1_pin_mux();
 254         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 255         if (read_eeprom() < 0)
 256                 puts("Could not get board ID.\n");
 257
 258         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 259
 260         return 0;
 261 }
 262
 263 #ifdef CONFIG_DRIVER_TI_CPSW
 264 static void cpsw_control(int enabled)
 265 {
 266         /* VTP can be added here */
 267
 268         return;
 269 }
 270
 271 static struct cpsw_slave_data cpsw_slaves[] = {
 272         {
 273                 .slave_reg_ofs  = 0x208,
 274                 .sliver_reg_ofs = 0xd80,
 275                 .phy_id         = 0,
 276         },
 277         {
 278                 .slave_reg_ofs  = 0x308,
 279                 .sliver_reg_ofs = 0xdc0,
 280                 .phy_id         = 1,
 281         },
 282 };
 283
 284 static struct cpsw_platform_data cpsw_data = {
 285         .mdio_base              = AM335X_CPSW_MDIO_BASE,
 286         .cpsw_base              = AM335X_CPSW_BASE,
 287         .mdio_div               = 0xff,
 288         .channels               = 8,
 289         .cpdma_reg_ofs          = 0x800,
 290         .slaves                 = 1,
 291         .slave_data             = cpsw_slaves,
 292         .ale_reg_ofs            = 0xd00,
 293         .ale_entries            = 1024,
 294         .host_port_reg_ofs      = 0x108,
 295         .hw_stats_reg_ofs       = 0x900,
 296         .mac_control            = (1 << 5),
 297         .control                = cpsw_control,
 298         .host_port_num          = 0,
 299         .version                = CPSW_CTRL_VERSION_2,
 300 };
 301
 302 int board_eth_init(bd_t *bis)
 303 {
 304         uint8_t mac_addr[6];
 305         uint32_t mac_hi, mac_lo;
 306
 307         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 308                 debug("<ethaddr> not set. Reading from E-fuse\n");
 309                 /* try reading mac address from efuse */
 310                 mac_lo = readl(&cdev->macid0l);
 311                 mac_hi = readl(&cdev->macid0h);
 312                 mac_addr[0] = mac_hi & 0xFF;
 313                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 314                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 315                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 316                 mac_addr[4] = mac_lo & 0xFF;
 317                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 318
 319                 if (is_valid_ether_addr(mac_addr))
 320                         eth_setenv_enetaddr("ethaddr", mac_addr);
 321                 else
 322                         return -1;
 323         }
 324
 325         if (board_is_bone()) {
 326                 enable_mii1_pin_mux();
 327                 writel(MII_MODE_ENABLE, &cdev->miisel);
 328                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 329                                 PHY_INTERFACE_MODE_MII;
 330         } else {
 331                 enable_rgmii1_pin_mux();
 332                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 333                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 334                                 PHY_INTERFACE_MODE_RGMII;
 335         }
 336
 337         return cpsw_register(&cpsw_data);
 338 }
 339 #endif