arch/arm/cpu/armv7/am33xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Common board functions for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <asm/arch/cpu.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/arch/omap.h>
  24 #include <asm/arch/ddr_defs.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/mmc_host_def.h>
  28 #include <asm/arch/common_def.h>
  29 #include <asm/io.h>
  30 #include <asm/omap_common.h>
  31 #include <asm/emif.h>
  32 #include <i2c.h>
  33 #include <miiphy.h>
  34 #include <cpsw.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  39 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
  40 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  41
  42 static const struct gpio_bank gpio_bank_am33xx[4] = {
  43         { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
  44         { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
  45         { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
  46         { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
  47 };
  48
  49 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
  50
  51 /* MII mode defines */
  52 #define MII_MODE_ENABLE         0x0
  53 #define RGMII_MODE_ENABLE       0xA
  54
  55 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  56
  57 /*
  58  * I2C Address of on-board EEPROM
  59  */
  60 #define I2C_BASE_BOARD_ADDR     0x50
  61
  62 #define NO_OF_MAC_ADDR          3
  63 #define ETH_ALEN                6
  64 #define NAME_LEN                8
  65
  66 struct am335x_baseboard_id {
  67         unsigned int  magic;
  68         char name[NAME_LEN];
  69         char version[4];
  70         char serial[12];
  71         char config[32];
  72         char mac_addr[NO_OF_MAC_ADDR][ETH_ALEN];
  73 };
  74
  75 static struct am335x_baseboard_id header;
  76
  77 static inline int board_is_bone(void)
  78 {
  79         return !strncmp(header.name, "A335BONE", NAME_LEN);
  80 }
  81
  82 /*
  83  * Read header information from EEPROM into global structure.
  84  */
  85 static int read_eeprom(void)
  86 {
  87         /* Check if baseboard eeprom is available */
  88         if (i2c_probe(I2C_BASE_BOARD_ADDR)) {
  89                 puts("Could not probe the EEPROM; something fundamentally "
  90                         "wrong on the I2C bus.\n");
  91                 return -ENODEV;
  92         }
  93
  94         /* read the eeprom using i2c */
  95         if (i2c_read(I2C_BASE_BOARD_ADDR, 0, 2, (uchar *)&header,
  96                                                         sizeof(header))) {
  97                 puts("Could not read the EEPROM; something fundamentally"
  98                         " wrong on the I2C bus.\n");
  99                 return -EIO;
 100         }
 101
 102         if (header.magic != 0xEE3355AA) {
 103                 /*
 104                  * read the eeprom using i2c again,
 105                  * but use only a 1 byte address
 106                  */
 107                 if (i2c_read(I2C_BASE_BOARD_ADDR, 0, 1, (uchar *)&header,
 108                                                         sizeof(header))) {
 109                         puts("Could not read the EEPROM; something "
 110                                 "fundamentally wrong on the I2C bus.\n");
 111                         return -EIO;
 112                 }
 113
 114                 if (header.magic != 0xEE3355AA) {
 115                         printf("Incorrect magic number (0x%x) in EEPROM\n",
 116                                         header.magic);
 117                         return -EINVAL;
 118                 }
 119         }
 120
 121         return 0;
 122 }
 123
 124 /* UART Defines */
 125 #ifdef CONFIG_SPL_BUILD
 126 #define UART_RESET              (0x1 << 1)
 127 #define UART_CLK_RUNNING_MASK   0x1
 128 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
 129 #endif
 130
 131 #ifdef CONFIG_SPL_BUILD
 132 /* Initialize timer */
 133 static void init_timer(void)
 134 {
 135         /* Reset the Timer */
 136         writel(0x2, (&timer_base->tscir));
 137
 138         /* Wait until the reset is done */
 139         while (readl(&timer_base->tiocp_cfg) & 1)
 140                 ;
 141
 142         /* Start the Timer */
 143         writel(0x1, (&timer_base->tclr));
 144 }
 145 #endif
 146
 147 /*
 148  * early system init of muxing and clocks.
 149  */
 150 void s_init(void)
 151 {
 152         /* WDT1 is already running when the bootloader gets control
 153          * Disable it to avoid "random" resets
 154          */
 155         writel(0xAAAA, &wdtimer->wdtwspr);
 156         while (readl(&wdtimer->wdtwwps) != 0x0)
 157                 ;
 158         writel(0x5555, &wdtimer->wdtwspr);
 159         while (readl(&wdtimer->wdtwwps) != 0x0)
 160                 ;
 161
 162 #ifdef CONFIG_SPL_BUILD
 163         /* Setup the PLLs and the clocks for the peripherals */
 164         pll_init();
 165
 166         /* UART softreset */
 167         u32 regVal;
 168
 169         enable_uart0_pin_mux();
 170
 171         regVal = readl(&uart_base->uartsyscfg);
 172         regVal |= UART_RESET;
 173         writel(regVal, &uart_base->uartsyscfg);
 174         while ((readl(&uart_base->uartsyssts) &
 175                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 176                 ;
 177
 178         /* Disable smart idle */
 179         regVal = readl(&uart_base->uartsyscfg);
 180         regVal |= UART_SMART_IDLE_EN;
 181         writel(regVal, &uart_base->uartsyscfg);
 182
 183         /* Initialize the Timer */
 184         init_timer();
 185
 186         preloader_console_init();
 187
 188         config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
 189 #endif
 190
 191         /* Enable MMC0 */
 192         enable_mmc0_pin_mux();
 193 }
 194
 195 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 196 int board_mmc_init(bd_t *bis)
 197 {
 198         return omap_mmc_init(0, 0, 0);
 199 }
 200 #endif
 201
 202 void setup_clocks_for_console(void)
 203 {
 204         /* Not yet implemented */
 205         return;
 206 }
 207
 208 /*
 209  * Basic board specific setup
 210  */
 211 int board_init(void)
 212 {
 213         enable_uart0_pin_mux();
 214
 215         enable_i2c0_pin_mux();
 216         enable_i2c1_pin_mux();
 217         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 218         if (read_eeprom() < 0)
 219                 puts("Could not get board ID.\n");
 220
 221         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 222
 223         return 0;
 224 }
 225
 226 #ifdef CONFIG_DRIVER_TI_CPSW
 227 static void cpsw_control(int enabled)
 228 {
 229         /* VTP can be added here */
 230
 231         return;
 232 }
 233
 234 static struct cpsw_slave_data cpsw_slaves[] = {
 235         {
 236                 .slave_reg_ofs  = 0x208,
 237                 .sliver_reg_ofs = 0xd80,
 238                 .phy_id         = 0,
 239         },
 240         {
 241                 .slave_reg_ofs  = 0x308,
 242                 .sliver_reg_ofs = 0xdc0,
 243                 .phy_id         = 1,
 244         },
 245 };
 246
 247 static struct cpsw_platform_data cpsw_data = {
 248         .mdio_base              = AM335X_CPSW_MDIO_BASE,
 249         .cpsw_base              = AM335X_CPSW_BASE,
 250         .mdio_div               = 0xff,
 251         .channels               = 8,
 252         .cpdma_reg_ofs          = 0x800,
 253         .slaves                 = 1,
 254         .slave_data             = cpsw_slaves,
 255         .ale_reg_ofs            = 0xd00,
 256         .ale_entries            = 1024,
 257         .host_port_reg_ofs      = 0x108,
 258         .hw_stats_reg_ofs       = 0x900,
 259         .mac_control            = (1 << 5),
 260         .control                = cpsw_control,
 261         .host_port_num          = 0,
 262         .version                = CPSW_CTRL_VERSION_2,
 263 };
 264
 265 int board_eth_init(bd_t *bis)
 266 {
 267         uint8_t mac_addr[6];
 268         uint32_t mac_hi, mac_lo;
 269
 270         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 271                 debug("<ethaddr> not set. Reading from E-fuse\n");
 272                 /* try reading mac address from efuse */
 273                 mac_lo = readl(&cdev->macid0l);
 274                 mac_hi = readl(&cdev->macid0h);
 275                 mac_addr[0] = mac_hi & 0xFF;
 276                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 277                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 278                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 279                 mac_addr[4] = mac_lo & 0xFF;
 280                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 281
 282                 if (is_valid_ether_addr(mac_addr))
 283                         eth_setenv_enetaddr("ethaddr", mac_addr);
 284                 else
 285                         return -1;
 286         }
 287
 288         if (board_is_bone()) {
 289                 enable_mii1_pin_mux();
 290                 writel(MII_MODE_ENABLE, &cdev->miisel);
 291                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 292                                 PHY_INTERFACE_MODE_MII;
 293         } else {
 294                 enable_rgmii1_pin_mux();
 295                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 296                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 297                                 PHY_INTERFACE_MODE_RGMII;
 298         }
 299
 300         return cpsw_register(&cpsw_data);
 301 }
 302 #endif