4 * clocks for AM33XX based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/hardware.h>
17 #define PRCM_MOD_EN 0x2
18 #define PRCM_FORCE_WAKEUP 0x2
19 #define PRCM_FUNCTL 0x0
21 #define PRCM_EMIF_CLK_ACTIVITY BIT(2)
22 #define PRCM_L3_GCLK_ACTIVITY BIT(4)
24 #define PLL_BYPASS_MODE 0x4
25 #define ST_MN_BYPASS 0x00000100
26 #define ST_DPLL_CLK 0x00000001
27 #define CLK_SEL_MASK 0x7ffff
28 #define CLK_DIV_MASK 0x1f
29 #define CLK_DIV2_MASK 0x7f
30 #define CLK_SEL_SHIFT 0x8
31 #define CLK_MODE_SEL 0x7
32 #define CLK_MODE_MASK 0xfffffff8
33 #define CLK_DIV_SEL 0xFFFFFFE0
34 #define CPGMAC0_IDLE 0x30000
35 #define DPLL_CLKDCOLDO_GATE_CTRL 0x300
37 #define OSC (V_OSCK/1000000)
39 #define MPUPLL_M CONFIG_SYS_MPUCLK
40 #define MPUPLL_N (OSC-1)
43 /* Core PLL Fdll = 1 GHZ, */
44 #define COREPLL_M 1000
45 #define COREPLL_N (OSC-1)
47 #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
48 #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
49 #define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
52 * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
53 * frequency needs to be set to 960 MHZ. Hence,
54 * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
57 #define PERPLL_N (OSC-1)
60 /* DDR Freq is 266 MHZ for now */
61 /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
63 #define DDRPLL_N (OSC-1)
66 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
67 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
68 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
69 const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
71 static void enable_interface_clocks(void)
73 /* Enable all the Interconnect Modules */
74 writel(PRCM_MOD_EN, &cmper->l3clkctrl);
75 while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
78 writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
79 while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
82 writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
83 while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
86 writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
87 while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
90 writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
91 while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
94 writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
95 while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
98 writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
99 while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
104 * Force power domain wake up transition
105 * Ensure that the corresponding interface clock is active before
106 * using the peripheral
108 static void power_domain_wkup_transition(void)
110 writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
111 writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
112 writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
113 writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
114 writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
118 * Enable the peripheral clock for required peripherals
120 static void enable_per_clocks(void)
122 /* Enable the control module though RBL would have done it*/
123 writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
124 while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
127 /* Enable the module clock */
128 writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
129 while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
132 /* Select the Master osc 24 MHZ as Timer2 clock source */
133 writel(0x1, &cmdpll->clktimer2clk);
136 writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
137 while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
141 #ifdef CONFIG_SERIAL2
142 writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
143 while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
145 #endif /* CONFIG_SERIAL2 */
148 #ifdef CONFIG_SERIAL3
149 writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
150 while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
152 #endif /* CONFIG_SERIAL3 */
155 #ifdef CONFIG_SERIAL4
156 writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
157 while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
159 #endif /* CONFIG_SERIAL4 */
162 #ifdef CONFIG_SERIAL5
163 writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
164 while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
166 #endif /* CONFIG_SERIAL5 */
169 #ifdef CONFIG_SERIAL6
170 writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
171 while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
173 #endif /* CONFIG_SERIAL6 */
176 writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
177 while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
181 writel(PRCM_MOD_EN, &cmper->elmclkctrl);
182 while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
186 writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
187 while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
191 writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
192 while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
196 writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
197 while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
201 writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
202 while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
206 writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
207 while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
211 writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
212 while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
216 writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
217 while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
221 writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
222 while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
226 writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
227 while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
231 writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
232 while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
236 writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
237 while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
241 void mpu_pll_config_val(int mpull_m)
243 u32 clkmode, clksel, div_m2;
245 clkmode = readl(&cmwkup->clkmoddpllmpu);
246 clksel = readl(&cmwkup->clkseldpllmpu);
247 div_m2 = readl(&cmwkup->divm2dpllmpu);
249 /* Set the PLL to bypass Mode */
250 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
251 while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
254 clksel = clksel & (~CLK_SEL_MASK);
255 clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
256 writel(clksel, &cmwkup->clkseldpllmpu);
258 div_m2 = div_m2 & ~CLK_DIV_MASK;
259 div_m2 = div_m2 | MPUPLL_M2;
260 writel(div_m2, &cmwkup->divm2dpllmpu);
262 clkmode = clkmode | CLK_MODE_SEL;
263 writel(clkmode, &cmwkup->clkmoddpllmpu);
265 while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
269 static void mpu_pll_config(void)
271 mpu_pll_config_val(CONFIG_SYS_MPUCLK);
274 static void core_pll_config(void)
276 u32 clkmode, clksel, div_m4, div_m5, div_m6;
278 clkmode = readl(&cmwkup->clkmoddpllcore);
279 clksel = readl(&cmwkup->clkseldpllcore);
280 div_m4 = readl(&cmwkup->divm4dpllcore);
281 div_m5 = readl(&cmwkup->divm5dpllcore);
282 div_m6 = readl(&cmwkup->divm6dpllcore);
284 /* Set the PLL to bypass Mode */
285 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
287 while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
290 clksel = clksel & (~CLK_SEL_MASK);
291 clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
292 writel(clksel, &cmwkup->clkseldpllcore);
294 div_m4 = div_m4 & ~CLK_DIV_MASK;
295 div_m4 = div_m4 | COREPLL_M4;
296 writel(div_m4, &cmwkup->divm4dpllcore);
298 div_m5 = div_m5 & ~CLK_DIV_MASK;
299 div_m5 = div_m5 | COREPLL_M5;
300 writel(div_m5, &cmwkup->divm5dpllcore);
302 div_m6 = div_m6 & ~CLK_DIV_MASK;
303 div_m6 = div_m6 | COREPLL_M6;
304 writel(div_m6, &cmwkup->divm6dpllcore);
306 clkmode = clkmode | CLK_MODE_SEL;
307 writel(clkmode, &cmwkup->clkmoddpllcore);
309 while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
313 static void per_pll_config(void)
315 u32 clkmode, clksel, div_m2;
317 clkmode = readl(&cmwkup->clkmoddpllper);
318 clksel = readl(&cmwkup->clkseldpllper);
319 div_m2 = readl(&cmwkup->divm2dpllper);
321 /* Set the PLL to bypass Mode */
322 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
324 while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
327 clksel = clksel & (~CLK_SEL_MASK);
328 clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
329 writel(clksel, &cmwkup->clkseldpllper);
331 div_m2 = div_m2 & ~CLK_DIV2_MASK;
332 div_m2 = div_m2 | PERPLL_M2;
333 writel(div_m2, &cmwkup->divm2dpllper);
335 clkmode = clkmode | CLK_MODE_SEL;
336 writel(clkmode, &cmwkup->clkmoddpllper);
338 while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
341 writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
344 void ddr_pll_config(unsigned int ddrpll_m)
346 u32 clkmode, clksel, div_m2;
348 clkmode = readl(&cmwkup->clkmoddpllddr);
349 clksel = readl(&cmwkup->clkseldpllddr);
350 div_m2 = readl(&cmwkup->divm2dpllddr);
352 /* Set the PLL to bypass Mode */
353 clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
354 writel(clkmode, &cmwkup->clkmoddpllddr);
356 /* Wait till bypass mode is enabled */
357 while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
361 clksel = clksel & (~CLK_SEL_MASK);
362 clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
363 writel(clksel, &cmwkup->clkseldpllddr);
365 div_m2 = div_m2 & CLK_DIV_SEL;
366 div_m2 = div_m2 | DDRPLL_M2;
367 writel(div_m2, &cmwkup->divm2dpllddr);
369 clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
370 writel(clkmode, &cmwkup->clkmoddpllddr);
372 /* Wait till dpll is locked */
373 while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
377 void enable_emif_clocks(void)
379 /* Enable the EMIF_FW Functional clock */
380 writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
381 /* Enable EMIF0 Clock */
382 writel(PRCM_MOD_EN, &cmper->emifclkctrl);
383 /* Poll if module is functional */
384 while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
389 * Configure the PLL/PRCM for necessary peripherals
397 /* Enable the required interconnect clocks */
398 enable_interface_clocks();
400 /* Power domain wake up transition */
401 power_domain_wkup_transition();
403 /* Enable the required peripherals */