arch/arm/cpu/armv7/am33xx/ddr2.c

   1 /*
   2  * ddr2.c
   3  * renamed from emif4.c Lothar Waßmann <LW@KARO-electronics.de>
   4  *
   5  * AM33XX emif4 configuration file
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <common.h>
  21 #include <asm/sizes.h>
  22 #include <asm/arch/cpu.h>
  23 #include <asm/arch/ddr_defs.h>
  24 #include <asm/arch/hardware.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/io.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
  31 struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
  32 struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  33
  34 #define EMIF_PHYCFG             0x2
  35 #define EMIF_SDMGT              0x80000000
  36 #define EMIF_SDRAM              0x00004650
  37 #define DDR2_RATIO              0x80
  38 #define CMD_FORCE               0x00
  39 #define CMD_DELAY               0x00
  40
  41 #define EMIF_READ_LATENCY       0x05
  42 #define EMIF_TIM1               0x0666B3D6
  43 #define EMIF_TIM2               0x143731DA
  44 #define EMIF_TIM3               0x00000347
  45 #define EMIF_SDCFG              0x43805332
  46 #define EMIF_SDREF              0x0000081a
  47 #define DDR2_DLL_LOCK_DIFF      0x0f
  48 #define DDR2_RD_DQS             0x12
  49 #define DDR2_PHY_FIFO_WE        0x80
  50
  51 #define DDR2_INVERT_CLKOUT      0x00
  52 #define DDR2_WR_DQS             0x00
  53 #define DDR2_PHY_WRLVL          0x00
  54 #define DDR2_PHY_GATELVL        0x00
  55 #define DDR2_PHY_WR_DATA        0x40
  56 #define PHY_RANK0_DELAY         0x01
  57 #define PHY_DLL_LOCK_DIFF       0x0
  58 #define DDR_IOCTRL_VALUE        0x18B
  59
  60 int dram_init(void)
  61 {
  62         /* dram_init must store complete ramsize in gd->ram_size */
  63         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  64                                 CONFIG_MAX_RAM_BANK_SIZE);
  65         debug("SDRAM size: 0x%08x\n", gd->ram_size);
  66         return 0;
  67 }
  68
  69 void dram_init_banksize(void)
  70 {
  71         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  72         gd->bd->bi_dram[0].size = gd->ram_size;
  73 }
  74
  75
  76 #ifdef CONFIG_SPL_BUILD
  77 static void data_macro_config(void)
  78 {
  79         struct ddr_data data;
  80
  81         data.datardsratio0 = ((DDR2_RD_DQS << 30) | (DDR2_RD_DQS << 20) |
  82                         (DDR2_RD_DQS << 10) | (DDR2_RD_DQS << 0));
  83         data.datardsratio1 = DDR2_RD_DQS >> 2;
  84         data.datawdsratio0 = ((DDR2_WR_DQS << 30) | (DDR2_WR_DQS << 20) |
  85                         (DDR2_WR_DQS << 10) | (DDR2_WR_DQS << 0));
  86         data.datawdsratio1 = DDR2_WR_DQS >> 2;
  87         data.datawiratio0 = ((DDR2_PHY_WRLVL << 30) | (DDR2_PHY_WRLVL << 20) |
  88                         (DDR2_PHY_WRLVL << 10) | (DDR2_PHY_WRLVL << 0));
  89         data.datawiratio1 = DDR2_PHY_WRLVL >> 2;
  90         data.datagiratio0 = ((DDR2_PHY_GATELVL << 30) | (DDR2_PHY_GATELVL << 20) |
  91                         (DDR2_PHY_GATELVL << 10) | (DDR2_PHY_GATELVL << 0));
  92         data.datagiratio1 = DDR2_PHY_GATELVL >> 2;
  93         data.datafwsratio0 = ((DDR2_PHY_FIFO_WE << 30) | (DDR2_PHY_FIFO_WE << 20) |
  94                         (DDR2_PHY_FIFO_WE << 10) | (DDR2_PHY_FIFO_WE << 0));
  95         data.datafwsratio1 = DDR2_PHY_FIFO_WE >> 2;
  96         data.datawrsratio0 = ((DDR2_PHY_WR_DATA << 30) | (DDR2_PHY_WR_DATA << 20) |
  97                         (DDR2_PHY_WR_DATA << 10) | (DDR2_PHY_WR_DATA << 0));
  98         data.datawrsratio1 = DDR2_PHY_WR_DATA >> 2;
  99         data.datadldiff0 = PHY_DLL_LOCK_DIFF;
 100
 101         config_ddr_data(0, &data);
 102         config_ddr_data(1, &data);
 103 }
 104
 105 static void cmd_macro_config(void)
 106 {
 107         struct cmd_control cmd;
 108
 109         cmd.cmd0csratio = DDR2_RATIO;
 110         cmd.cmd0csforce = CMD_FORCE;
 111         cmd.cmd0csdelay = CMD_DELAY;
 112         cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF;
 113         cmd.cmd0iclkout = DDR2_INVERT_CLKOUT;
 114
 115         cmd.cmd1csratio = DDR2_RATIO;
 116         cmd.cmd1csforce = CMD_FORCE;
 117         cmd.cmd1csdelay = CMD_DELAY;
 118         cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF;
 119         cmd.cmd1iclkout = DDR2_INVERT_CLKOUT;
 120
 121         cmd.cmd2csratio = DDR2_RATIO;
 122         cmd.cmd2csforce = CMD_FORCE;
 123         cmd.cmd2csdelay = CMD_DELAY;
 124         cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF;
 125         cmd.cmd2iclkout = DDR2_INVERT_CLKOUT;
 126
 127         config_cmd_ctrl(&cmd);
 128 }
 129
 130 static void config_vtp(void)
 131 {
 132         writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
 133                         &vtpreg->vtp0ctrlreg);
 134         writel(readl(&vtpreg->vtp0ctrlreg) & ~VTP_CTRL_START_EN,
 135                         &vtpreg->vtp0ctrlreg);
 136         writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
 137                         &vtpreg->vtp0ctrlreg);
 138
 139         /* Poll for READY */
 140         while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
 141                         VTP_CTRL_READY)
 142                 ;
 143 }
 144
 145 static void config_emif_ddr2(void)
 146 {
 147         int i;
 148         int ret;
 149         struct sdram_config cfg;
 150         struct sdram_timing tmg;
 151         struct ddr_phy_control phyc;
 152
 153 debug("%s\n", __func__);
 154
 155         /* Program EMIF0 CFG Registers */
 156         phyc.reg = EMIF_READ_LATENCY;
 157         phyc.reg_sh = EMIF_READ_LATENCY;
 158         phyc.reg2 = EMIF_READ_LATENCY;
 159
 160         tmg.time1 = EMIF_TIM1;
 161         tmg.time1_sh = EMIF_TIM1;
 162         tmg.time2 = EMIF_TIM2;
 163         tmg.time2_sh = EMIF_TIM2;
 164         tmg.time3 = EMIF_TIM3;
 165         tmg.time3_sh = EMIF_TIM3;
 166
 167         cfg.sdrcr = EMIF_SDCFG;
 168         cfg.sdrcr2 = EMIF_SDCFG;
 169         cfg.refresh = 0x00004650;
 170         cfg.refresh_sh = 0x00004650;
 171
 172         /* Program EMIF instance */
 173         ret = config_ddr_phy(&phyc);
 174         if (ret < 0)
 175                 printf("Couldn't configure phyc\n");
 176
 177         ret = config_sdram(&cfg);
 178         if (ret < 0)
 179                 printf("Couldn't configure SDRAM\n");
 180
 181         ret = set_sdram_timings(&tmg);
 182         if (ret < 0)
 183                 printf("Couldn't configure timings\n");
 184
 185         /* Delay */
 186         for (i = 0; i < 5000; i++)
 187                 ;
 188
 189         cfg.refresh = EMIF_SDREF;
 190         cfg.refresh_sh = EMIF_SDREF;
 191         cfg.sdrcr = EMIF_SDCFG;
 192         cfg.sdrcr2 = EMIF_SDCFG;
 193
 194         ret = config_sdram(&cfg);
 195         if (ret < 0)
 196                 printf("Couldn't configure SDRAM\n");
 197 }
 198
 199 void config_ddr(void)
 200 {
 201         struct ddr_ioctrl ioctrl;
 202
 203 debug("%s\n", __func__);
 204
 205         enable_emif_clocks();
 206
 207         config_vtp();
 208
 209         cmd_macro_config();
 210
 211         data_macro_config();
 212
 213         writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
 214         writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
 215
 216         ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
 217         ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
 218         ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
 219         ioctrl.data1ctl = DDR_IOCTRL_VALUE;
 220         ioctrl.data2ctl = DDR_IOCTRL_VALUE;
 221
 222         config_io_ctrl(&ioctrl);
 223
 224         writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
 225         writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);
 226
 227         config_emif_ddr2();
 228 }
 229 #endif