arch/arm/cpu/armv7/keystone/init.c

   1 /*
   2  * Keystone2: Architecture initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <ns16550.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/msmc.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/psc_defs.h>
  17
  18 void chip_configuration_unlock(void)
  19 {
  20         __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  21         __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  22 }
  23
  24 #ifdef CONFIG_SOC_K2L
  25 void osr_init(void)
  26 {
  27         u32 i;
  28         u32 j;
  29         u32 val;
  30         u32 base = KS2_OSR_CFG_BASE;
  31         u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
  32
  33         /* Enable the OSR clock domain */
  34         psc_enable_module(KS2_LPSC_OSR);
  35
  36         /* Disable OSR ECC check for all the ram banks */
  37         for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
  38                 val = i | KS2_OSR_ECC_VEC_TRIG_RD |
  39                         (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
  40
  41                 writel(val , base + KS2_OSR_ECC_VEC);
  42
  43                 /**
  44                  * wait till read is done.
  45                  * Print should be added after earlyprintk support is added.
  46                  */
  47                 for (j = 0; j < 10000; j++) {
  48                         val = readl(base + KS2_OSR_ECC_VEC);
  49                         if (val & KS2_OSR_ECC_VEC_RD_DONE)
  50                                 break;
  51                 }
  52
  53                 ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
  54                                                 KS2_OSR_ECC_CTRL_CHK;
  55
  56                 writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
  57                 writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
  58         }
  59
  60         /* Reset OSR memory to all zeros */
  61         for (i = 0; i < KS2_OSR_SIZE; i += 4)
  62                 writel(0, KS2_OSR_DATA_BASE + i);
  63
  64         /* Enable OSR ECC check for all the ram banks */
  65         for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
  66                 writel(ecc_ctrl[i] |
  67                        KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
  68 }
  69 #endif
  70
  71 int arch_cpu_init(void)
  72 {
  73         chip_configuration_unlock();
  74         icache_enable();
  75
  76         msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
  77         msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
  78         msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
  79         msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
  80 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
  81         msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
  82 #endif
  83 #ifdef CONFIG_SOC_K2L
  84         osr_init();
  85 #endif
  86
  87         /*
  88          * just initialise the COM2 port so that TI specific
  89          * UART register PWREMU_MGMT is initialized. Linux UART
  90          * driver doesn't handle this.
  91          */
  92         NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
  93                      CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  94
  95         return 0;
  96 }
  97
  98 void reset_cpu(ulong addr)
  99 {
 100         volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
 101         u32 tmp;
 102
 103         tmp = *rstctrl & KS2_RSTCTRL_MASK;
 104         *rstctrl = tmp | KS2_RSTCTRL_KEY;
 105
 106         *rstctrl &= KS2_RSTCTRL_SWRST;
 107
 108         for (;;)
 109                 ;
 110 }
 111
 112 void enable_caches(void)
 113 {
 114 #ifndef CONFIG_SYS_DCACHE_OFF
 115         /* Enable D-cache. I-cache is already enabled in start.S */
 116         dcache_enable();
 117 #endif
 118 }