arch/arm/cpu/armv7/ls102xa/fdt.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <libfdt.h>
   9 #include <fdt_support.h>
  10 #include <asm/io.h>
  11 #include <asm/processor.h>
  12 #include <asm/arch/clock.h>
  13 #include <linux/ctype.h>
  14 #ifdef CONFIG_FSL_ESDHC
  15 #include <fsl_esdhc.h>
  16 #endif
  17 #include <tsec.h>
  18 #include <asm/arch/immap_ls102xa.h>
  19 #include <fsl_sec.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 void ft_fixup_enet_phy_connect_type(void *fdt)
  24 {
  25         struct eth_device *dev;
  26         struct tsec_private *priv;
  27         const char *enet_path, *phy_path;
  28         char enet[16];
  29         char phy[16];
  30         int phy_node;
  31         int i = 0;
  32         uint32_t ph;
  33
  34         while ((dev = eth_get_dev_by_index(i++)) != NULL) {
  35                 if (strstr(dev->name, "eTSEC1")) {
  36                         strcpy(enet, "ethernet0");
  37                         strcpy(phy, "enet0_rgmii_phy");
  38                 } else if (strstr(dev->name, "eTSEC2")) {
  39                         strcpy(enet, "ethernet1");
  40                         strcpy(phy, "enet1_rgmii_phy");
  41                 } else if (strstr(dev->name, "eTSEC3")) {
  42                         strcpy(enet, "ethernet2");
  43                         strcpy(phy, "enet2_rgmii_phy");
  44                 } else {
  45                         continue;
  46                 }
  47
  48                 priv = dev->priv;
  49                 if (priv->flags & TSEC_SGMII)
  50                         continue;
  51
  52                 enet_path = fdt_get_alias(fdt, enet);
  53                 if (!enet_path)
  54                         continue;
  55
  56                 phy_path = fdt_get_alias(fdt, phy);
  57                 if (!phy_path)
  58                         continue;
  59
  60                 phy_node = fdt_path_offset(fdt, phy_path);
  61                 if (phy_node < 0)
  62                         continue;
  63
  64                 ph = fdt_create_phandle(fdt, phy_node);
  65                 if (ph)
  66                         do_fixup_by_path_u32(fdt, enet_path,
  67                                              "phy-handle", ph, 1);
  68
  69                 do_fixup_by_path(fdt, enet_path, "phy-connection-type",
  70                                  phy_string_for_interface(
  71                                  PHY_INTERFACE_MODE_RGMII_ID),
  72                                  sizeof(phy_string_for_interface(
  73                                  PHY_INTERFACE_MODE_RGMII_ID)),
  74                                  1);
  75         }
  76 }
  77
  78 void ft_cpu_setup(void *blob, bd_t *bd)
  79 {
  80         int off;
  81         int val;
  82         const char *sysclk_path;
  83         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  84         unsigned int svr;
  85         svr = in_be32(&gur->svr);
  86
  87         unsigned long busclk = get_bus_freq(0);
  88
  89         /* delete crypto node if not on an E-processor */
  90         if (!IS_E_PROCESSOR(svr))
  91                 fdt_fixup_crypto_node(blob, 0);
  92 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  93         else {
  94                 ccsr_sec_t __iomem *sec;
  95
  96                 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
  97                 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
  98         }
  99 #endif
 100
 101         fdt_fixup_ethernet(blob);
 102
 103         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 104         while (off != -FDT_ERR_NOTFOUND) {
 105                 val = gd->cpu_clk;
 106                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 107                 off = fdt_node_offset_by_prop_value(blob, off,
 108                                                     "device_type", "cpu", 4);
 109         }
 110
 111         do_fixup_by_prop_u32(blob, "device_type", "soc",
 112                              4, "bus-frequency", busclk, 1);
 113
 114         ft_fixup_enet_phy_connect_type(blob);
 115
 116 #ifdef CONFIG_SYS_NS16550
 117         do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
 118                                "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 119 #endif
 120
 121         sysclk_path = fdt_get_alias(blob, "sysclk");
 122         if (sysclk_path)
 123                 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
 124                                      CONFIG_SYS_CLK_FREQ, 1);
 125         do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
 126                                "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 127
 128 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
 129 #define UBOOT_HEAD_LEN  0x1000
 130         /*
 131          * Reserved memory in SD boot deep sleep case.
 132          * Second stage uboot binary and malloc space should be reserved.
 133          * If the memory they occupied has not been reserved, then this
 134          * space would be used by kernel and overwritten in uboot when
 135          * deep sleep resume, which cause deep sleep failed.
 136          * Since second uboot binary has a head, that space need to be
 137          * reserved either(assuming its size is less than 0x1000).
 138          */
 139         off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
 140                         CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
 141                         UBOOT_HEAD_LEN);
 142         if (off < 0)
 143                 printf("Failed to reserve memory for SD boot deep sleep: %s\n",
 144                        fdt_strerror(off));
 145 #endif
 146
 147 #if defined(CONFIG_FSL_ESDHC)
 148         fdt_fixup_esdhc(blob, bd);
 149 #endif
 150
 151         /*
 152          * platform bus clock = system bus clock/2
 153          * Here busclk = system bus clock
 154          * We are using the platform bus clock as 1588 Timer reference
 155          * clock source select
 156          */
 157         do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
 158                                "timer-frequency", busclk / 2, 1);
 159
 160         /*
 161          * clock-freq should change to clock-frequency and
 162          * flexcan-v1.0 should change to p1010-flexcan respectively
 163          * in the future.
 164          */
 165         do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
 166                                "clock_freq", busclk / 2, 1);
 167
 168         do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
 169                                "clock-frequency", busclk / 2, 1);
 170
 171         do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
 172                                "clock-frequency", busclk / 2, 1);
 173
 174 #ifdef CONFIG_QSPI_BOOT
 175         off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
 176                                             CONFIG_SYS_IFC_ADDR);
 177         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 178 #else
 179         off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
 180                                             QSPI0_BASE_ADDR);
 181         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 182         off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
 183                                             DSPI1_BASE_ADDR);
 184         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 185 #endif
 186 }