arch/arm/cpu/armv7/mx5/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/sys_proto.h>
  30
  31 #include <asm/errno.h>
  32 #include <asm/io.h>
  33
  34 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
  35 #error "CPU_TYPE not defined"
  36 #endif
  37
  38 u32 get_cpu_rev(void)
  39 {
  40 #ifdef CONFIG_MX51
  41         int system_rev = 0x51000;
  42 #else
  43         int system_rev = 0x53000;
  44 #endif
  45         int reg = __raw_readl(ROM_SI_REV);
  46
  47 #if defined(CONFIG_MX51)
  48         switch (reg) {
  49         case 0x02:
  50                 system_rev |= CHIP_REV_1_1;
  51                 break;
  52         case 0x10:
  53                 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
  54                         system_rev |= CHIP_REV_2_5;
  55                 else
  56                         system_rev |= CHIP_REV_2_0;
  57                 break;
  58         case 0x20:
  59                 system_rev |= CHIP_REV_3_0;
  60                 break;
  61         default:
  62                 system_rev |= CHIP_REV_1_0;
  63                 break;
  64         }
  65 #else
  66         if (reg < 0x20)
  67                 system_rev |= CHIP_REV_1_0;
  68         else
  69                 system_rev |= reg;
  70 #endif
  71         return system_rev;
  72 }
  73
  74 #if defined(CONFIG_FEC_MXC)
  75 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  76 {
  77         int i;
  78         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  79         struct fuse_bank *bank = &iim->bank[1];
  80         struct fuse_bank1_regs *fuse =
  81                         (struct fuse_bank1_regs *)bank->fuse_regs;
  82
  83         for (i = 0; i < 6; i++)
  84                 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
  85 }
  86 #endif
  87
  88 void set_chipselect_size(int const cs_size)
  89 {
  90         unsigned int reg;
  91         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  92         reg = readl(&iomuxc_regs->gpr1);
  93
  94         switch (cs_size) {
  95         case CS0_128:
  96                 reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
  97                 reg |= 0x5;
  98                 break;
  99         case CS0_64M_CS1_64M:
 100                 reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
 101                 reg |= 0x1B;
 102                 break;
 103         case CS0_64M_CS1_32M_CS2_32M:
 104                 reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
 105                 reg |= 0x4B;
 106                 break;
 107         case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
 108                 reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
 109                 reg |= 0x249;
 110                 break;
 111         default:
 112                 printf("Unknown chip select size: %d\n", cs_size);
 113                 break;
 114         }
 115
 116         writel(reg, &iomuxc_regs->gpr1);
 117 }