3 * Common functions for OMAP4/5 based boards
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/arch/sys_proto.h>
33 #include <asm/sizes.h>
35 #include <asm/omap_common.h>
36 #include <linux/compiler.h>
37 #include <asm/cache.h>
38 #include <asm/system.h>
40 #define ARMV7_DCACHE_WRITEBACK 0xe
41 #define ARMV7_DOMAIN_CLIENT 1
42 #define ARMV7_DOMAIN_MASK (0x3 << 0)
44 DECLARE_GLOBAL_DATA_PTR;
46 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
49 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
51 for (i = 0; i < size; i++, pad++)
52 writew(pad->val, base + pad->offset);
55 static void set_mux_conf_regs(void)
57 switch (omap_hw_init_context()) {
58 case OMAP_INIT_CONTEXT_SPL:
59 set_muxconf_regs_essential();
61 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
62 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
63 set_muxconf_regs_non_essential();
66 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
67 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
68 set_muxconf_regs_essential();
69 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
70 set_muxconf_regs_non_essential();
81 /* Read Main ID Register (MIDR) */
82 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
87 static void omap_rev_string(void)
89 u32 omap_rev = omap_revision();
90 u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
91 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
92 u32 major_rev = (omap_rev & 0x00000F00) >> 8;
93 u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
99 printf("%x ES%x.%x\n", omap_variant, major_rev,
103 #ifdef CONFIG_SPL_BUILD
104 void spl_display_print(void)
110 void __weak srcomp_enable(void)
114 #ifdef CONFIG_ARCH_CPU_INIT
116 * SOC specific cpu init
118 int arch_cpu_init(void)
120 save_omap_boot_params();
123 #endif /* CONFIG_ARCH_CPU_INIT */
127 * Description: Does early system init of watchdog, muxing, andclocks
128 * Watchdog disable is done always. For the rest what gets done
129 * depends on the boot mode in which this function is executed
130 * 1. s_init of SPL running from SRAM
131 * 2. s_init of U-Boot running from FLASH
132 * 3. s_init of U-Boot loaded to SDRAM by SPL
133 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
134 * Configuration Header feature
135 * Please have a look at the respective functions to see what gets
136 * done in each of these cases
137 * This function is called with SRAM stack.
142 * Save the boot parameters passed from romcode.
143 * We cannot delay the saving further than this,
144 * to prevent overwrites.
146 #ifdef CONFIG_SPL_BUILD
147 save_omap_boot_params();
149 init_omap_revision();
152 #ifdef CONFIG_SPL_BUILD
153 if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
154 force_emif_self_refresh();
158 #ifdef CONFIG_SPL_BUILD
160 setup_clocks_for_console();
164 preloader_console_init();
168 #ifdef CONFIG_SPL_BUILD
169 /* For regular u-boot sdram_init() is called from dram_init() */
175 * Routine: wait_for_command_complete
176 * Description: Wait for posting to finish on watchdog
178 void wait_for_command_complete(struct watchdog *wd_base)
182 pending = readl(&wd_base->wwps);
187 * Routine: watchdog_init
188 * Description: Shut down watch dogs
190 void watchdog_init(void)
192 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
194 writel(WD_UNLOCK1, &wd2_base->wspr);
195 wait_for_command_complete(wd2_base);
196 writel(WD_UNLOCK2, &wd2_base->wspr);
201 * This function finds the SDRAM size available in the system
202 * based on DMM section configurations
203 * This is needed because the size of memory installed may be
204 * different on different versions of the board
206 u32 omap_sdram_size(void)
208 u32 section, i, valid;
209 u64 sdram_start = 0, sdram_end = 0, addr,
210 size, total_size = 0, trap_size = 0;
212 for (i = 0; i < 4; i++) {
213 section = __raw_readl(DMM_BASE + i*4);
214 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
215 (EMIF_SDRC_ADDRSPC_SHIFT);
216 addr = section & EMIF_SYS_ADDR_MASK;
218 /* See if the address is valid */
219 if ((addr >= DRAM_ADDR_SPACE_START) &&
220 (addr < DRAM_ADDR_SPACE_END)) {
221 size = ((section & EMIF_SYS_SIZE_MASK) >>
222 EMIF_SYS_SIZE_SHIFT);
226 if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
227 if (!sdram_start || (addr < sdram_start))
229 if (!sdram_end || ((addr + size) > sdram_end))
230 sdram_end = addr + size;
238 total_size = (sdram_end - sdram_start) - (trap_size);
246 * Description: sets uboots idea of sdram size
251 gd->ram_size = omap_sdram_size();
256 * Print board information
260 puts(sysinfo.board_string);
265 * get_device_type(): tell if GP/HS/EMU/TST
267 u32 get_device_type(void)
269 return (readl((*ctrl)->control_status) &
270 (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
274 * Print CPU information
276 int print_cpuinfo(void)
283 #ifndef CONFIG_SYS_DCACHE_OFF
284 void enable_caches(void)
286 /* Enable D-cache. I-cache is already enabled in start.S */
290 void dram_bank_mmu_setup(int bank)
295 u32 start = bd->bi_dram[bank].start >> 20;
296 u32 size = bd->bi_dram[bank].size >> 20;
297 u32 end = start + size;
299 debug("%s: bank: %d\n", __func__, bank);
300 for (i = start; i < end; i++)
301 set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
305 void arm_init_domains(void)
311 * Set DOMAIN to client access so that all permissions
312 * set in pagetables are validated by the mmu.
314 reg &= ~ARMV7_DOMAIN_MASK;
315 reg |= ARMV7_DOMAIN_CLIENT;