arch/arm/cpu/armv7/omap3/sys_info.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *      Manikandan Pillai <mani.pillai@ti.com>
   7  *
   8  * Derived from Beagle Board and 3430 SDP code by
   9  *      Richard Woodruff <r-woodruff2@ti.com>
  10  *      Syed Mohammed Khasim <khasim@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/mem.h>       /* get mem tables */
  31 #include <asm/arch/sys_proto.h>
  32 #include <i2c.h>
  33
  34 extern omap3_sysinfo sysinfo;
  35 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  36
  37 #ifdef CONFIG_DISPLAY_CPUINFO
  38 static char *rev_s[CPU_3XX_MAX_REV] = {
  39                                 "1.0",
  40                                 "2.0",
  41                                 "2.1",
  42                                 "3.0",
  43                                 "3.1",
  44                                 "UNKNOWN",
  45                                 "UNKNOWN",
  46                                 "3.1.2"};
  47
  48 /* this is the revision table for 37xx CPUs */
  49 static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
  50                                 "1.0",
  51                                 "1.1",
  52                                 "1.2"};
  53 #endif /* CONFIG_DISPLAY_CPUINFO */
  54
  55 /*****************************************************************
  56  * dieid_num_r(void) - read and set die ID
  57  *****************************************************************/
  58 void dieid_num_r(void)
  59 {
  60         struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
  61         char *uid_s, die_id[34];
  62         u32 id[4];
  63
  64         memset(die_id, 0, sizeof(die_id));
  65
  66         uid_s = getenv("dieid#");
  67
  68         if (uid_s == NULL) {
  69                 id[3] = readl(&id_base->die_id_0);
  70                 id[2] = readl(&id_base->die_id_1);
  71                 id[1] = readl(&id_base->die_id_2);
  72                 id[0] = readl(&id_base->die_id_3);
  73                 sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
  74                 setenv("dieid#", die_id);
  75                 uid_s = die_id;
  76         }
  77
  78         printf("Die ID #%s\n", uid_s);
  79 }
  80
  81 /******************************************
  82  * get_cpu_type(void) - extract cpu info
  83  ******************************************/
  84 u32 get_cpu_type(void)
  85 {
  86         return readl(&ctrl_base->ctrl_omap_stat);
  87 }
  88
  89 /******************************************
  90  * get_cpu_id(void) - extract cpu id
  91  * returns 0 for ES1.0, cpuid otherwise
  92  ******************************************/
  93 u32 get_cpu_id(void)
  94 {
  95         struct ctrl_id *id_base;
  96         u32 cpuid = 0;
  97
  98         /*
  99          * On ES1.0 the IDCODE register is not exposed on L4
 100          * so using CPU ID to differentiate between ES1.0 and > ES1.0.
 101          */
 102         __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
 103         if ((cpuid & 0xf) == 0x0) {
 104                 return 0;
 105         } else {
 106                 /* Decode the IDs on > ES1.0 */
 107                 id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
 108
 109                 cpuid = readl(&id_base->idcode);
 110         }
 111
 112         return cpuid;
 113 }
 114
 115 /******************************************
 116  * get_cpu_family(void) - extract cpu info
 117  ******************************************/
 118 u32 get_cpu_family(void)
 119 {
 120         u16 hawkeye;
 121         u32 cpu_family;
 122         u32 cpuid = get_cpu_id();
 123
 124         if (cpuid == 0)
 125                 return CPU_OMAP34XX;
 126
 127         hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
 128         switch (hawkeye) {
 129         case HAWKEYE_OMAP34XX:
 130                 cpu_family = CPU_OMAP34XX;
 131                 break;
 132         case HAWKEYE_AM35XX:
 133                 cpu_family = CPU_AM35XX;
 134                 break;
 135         case HAWKEYE_OMAP36XX:
 136                 cpu_family = CPU_OMAP36XX;
 137                 break;
 138         default:
 139                 cpu_family = CPU_OMAP34XX;
 140         }
 141
 142         return cpu_family;
 143 }
 144
 145 /******************************************
 146  * get_cpu_rev(void) - extract version info
 147  ******************************************/
 148 u32 get_cpu_rev(void)
 149 {
 150         u32 cpuid = get_cpu_id();
 151
 152         if (cpuid == 0)
 153                 return CPU_3XX_ES10;
 154         else
 155                 return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
 156 }
 157
 158 /*****************************************************************
 159  * get_sku_id(void) - read sku_id to get info on max clock rate
 160  *****************************************************************/
 161 u32 get_sku_id(void)
 162 {
 163         struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
 164         return readl(&id_base->sku_id) & SKUID_CLK_MASK;
 165 }
 166
 167 /***************************************************************************
 168  *  get_gpmc0_base() - Return current address hardware will be
 169  *     fetching from. The below effectively gives what is correct, its a bit
 170  *   mis-leading compared to the TRM.  For the most general case the mask
 171  *   needs to be also taken into account this does work in practice.
 172  *   - for u-boot we currently map:
 173  *       -- 0 to nothing,
 174  *       -- 4 to flash
 175  *       -- 8 to enent
 176  *       -- c to wifi
 177  ****************************************************************************/
 178 u32 get_gpmc0_base(void)
 179 {
 180         u32 b;
 181
 182         b = readl(&gpmc_cfg->cs[0].config7);
 183         b &= 0x1F;              /* keep base [5:0] */
 184         b = b << 24;            /* ret 0x0b000000 */
 185         return b;
 186 }
 187
 188 /*******************************************************************
 189  * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
 190  *******************************************************************/
 191 u32 get_gpmc0_width(void)
 192 {
 193         return WIDTH_16BIT;
 194 }
 195
 196 /*************************************************************************
 197  * get_board_rev() - setup to pass kernel board revision information
 198  * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
 199  *************************************************************************/
 200 u32 get_board_rev(void)
 201 {
 202         return 0x20;
 203 }
 204
 205 /********************************************************
 206  *  get_base(); get upper addr of current execution
 207  *******************************************************/
 208 u32 get_base(void)
 209 {
 210         u32 val;
 211
 212         __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
 213         val &= 0xF0000000;
 214         val >>= 28;
 215         return val;
 216 }
 217
 218 /********************************************************
 219  *  is_running_in_flash() - tell if currently running in
 220  *  FLASH.
 221  *******************************************************/
 222 u32 is_running_in_flash(void)
 223 {
 224         if (get_base() < 4)
 225                 return 1;       /* in FLASH */
 226
 227         return 0;               /* running in SRAM or SDRAM */
 228 }
 229
 230 /********************************************************
 231  *  is_running_in_sram() - tell if currently running in
 232  *  SRAM.
 233  *******************************************************/
 234 u32 is_running_in_sram(void)
 235 {
 236         if (get_base() == 4)
 237                 return 1;       /* in SRAM */
 238
 239         return 0;               /* running in FLASH or SDRAM */
 240 }
 241
 242 /********************************************************
 243  *  is_running_in_sdram() - tell if currently running in
 244  *  SDRAM.
 245  *******************************************************/
 246 u32 is_running_in_sdram(void)
 247 {
 248         if (get_base() > 4)
 249                 return 1;       /* in SDRAM */
 250
 251         return 0;               /* running in SRAM or FLASH */
 252 }
 253
 254 /***************************************************************
 255  *  get_boot_type() - Is this an XIP type device or a stream one
 256  *  bits 4-0 specify type. Bit 5 says mem/perif
 257  ***************************************************************/
 258 u32 get_boot_type(void)
 259 {
 260         return (readl(&ctrl_base->status) & SYSBOOT_MASK);
 261 }
 262
 263 /*************************************************************
 264  *  get_device_type(): tell if GP/HS/EMU/TST
 265  *************************************************************/
 266 u32 get_device_type(void)
 267 {
 268         return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
 269 }
 270
 271 #ifdef CONFIG_DISPLAY_CPUINFO
 272 /**
 273  * Print CPU information
 274  */
 275 int print_cpuinfo (void)
 276 {
 277         char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
 278
 279         switch (get_cpu_family()) {
 280         case CPU_OMAP34XX:
 281                 cpu_family_s = "OMAP";
 282                 switch (get_cpu_type()) {
 283                 case OMAP3503:
 284                         cpu_s = "3503";
 285                         break;
 286                 case OMAP3515:
 287                         cpu_s = "3515";
 288                         break;
 289                 case OMAP3525:
 290                         cpu_s = "3525";
 291                         break;
 292                 case OMAP3530:
 293                         cpu_s = "3530";
 294                         break;
 295                 default:
 296                         cpu_s = "35XX";
 297                         break;
 298                 }
 299                 if ((get_cpu_rev() >= CPU_3XX_ES31) &&
 300                     (get_sku_id() == SKUID_CLK_720MHZ))
 301                         max_clk = "720 mHz";
 302                 else
 303                         max_clk = "600 mHz";
 304
 305                 break;
 306         case CPU_AM35XX:
 307                 cpu_family_s = "AM";
 308                 switch (get_cpu_type()) {
 309                 case AM3505:
 310                         cpu_s = "3505";
 311                         break;
 312                 case AM3517:
 313                         cpu_s = "3517";
 314                         break;
 315                 default:
 316                         cpu_s = "35XX";
 317                         break;
 318                 }
 319                 max_clk = "600 Mhz";
 320                 break;
 321         case CPU_OMAP36XX:
 322                 cpu_family_s = "OMAP";
 323                 switch (get_cpu_type()) {
 324                 case OMAP3730:
 325                         cpu_s = "3630/3730";
 326                         break;
 327                 default:
 328                         cpu_s = "36XX/37XX";
 329                         break;
 330                 }
 331                 max_clk = "1 Ghz";
 332                 break;
 333         default:
 334                 cpu_family_s = "OMAP";
 335                 cpu_s = "35XX";
 336                 max_clk = "600 Mhz";
 337         }
 338
 339         switch (get_device_type()) {
 340         case TST_DEVICE:
 341                 sec_s = "TST";
 342                 break;
 343         case EMU_DEVICE:
 344                 sec_s = "EMU";
 345                 break;
 346         case HS_DEVICE:
 347                 sec_s = "HS";
 348                 break;
 349         case GP_DEVICE:
 350                 sec_s = "GP";
 351                 break;
 352         default:
 353                 sec_s = "?";
 354         }
 355
 356         if (CPU_OMAP36XX == get_cpu_family())
 357                 printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
 358                         cpu_family_s, cpu_s, sec_s,
 359                         rev_s_37xx[get_cpu_rev()], max_clk);
 360         else
 361                 printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
 362                         cpu_family_s, cpu_s, sec_s,
 363                         rev_s[get_cpu_rev()], max_clk);
 364
 365         return 0;
 366 }
 367 #endif  /* CONFIG_DISPLAY_CPUINFO */