arch/arm/cpu/armv7/omap5/sdram.c

   1 /*
   2  * Timing and Organization details of the ddr device parts used in OMAP5
   3  * EVM
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  * Sricharan R <r.sricharan@ti.com>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <asm/emif.h>
  31 #include <asm/arch/sys_proto.h>
  32
  33 /*
  34  * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  35  * EVM. Since the parts used and geometry are identical for
  36  * evm for a given OMAP5 revision, this information is kept
  37  * here instead of being in board directory. However the key functions
  38  * exported are weakly linked so that they can be over-ridden in the board
  39  * directory if there is a OMAP5 board in the future that uses a different
  40  * memory device or geometry.
  41  *
  42  * For any new board with different memory devices over-ride one or more
  43  * of the following functions as per the CONFIG flags you intend to enable:
  44  * - emif_get_reg_dump()
  45  * - emif_get_dmm_regs()
  46  * - emif_get_device_details()
  47  * - emif_get_device_timings()
  48  */
  49
  50 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  51 const struct emif_regs emif_regs_532_mhz_2cs = {
  52         .sdram_config_init              = 0x80800EBA,
  53         .sdram_config                   = 0x808022BA,
  54         .ref_ctrl                       = 0x0000081A,
  55         .sdram_tim1                     = 0x772F6873,
  56         .sdram_tim2                     = 0x304a129a,
  57         .sdram_tim3                     = 0x02f7e45f,
  58         .read_idle_ctrl                 = 0x00050000,
  59         .zq_config                      = 0x000b3215,
  60         .temp_alert_config              = 0x08000a05,
  61         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  62         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  63         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  64         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  65         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  66         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  67         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  68 };
  69
  70 const struct emif_regs emif_regs_266_mhz_2cs = {
  71         .sdram_config_init              = 0x80800EBA,
  72         .sdram_config                   = 0x808022BA,
  73         .ref_ctrl                       = 0x0000040D,
  74         .sdram_tim1                     = 0x2A86B419,
  75         .sdram_tim2                     = 0x1025094A,
  76         .sdram_tim3                     = 0x026BA22F,
  77         .read_idle_ctrl                 = 0x00050000,
  78         .zq_config                      = 0x000b3215,
  79         .temp_alert_config              = 0x08000a05,
  80         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  81         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  82         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  83         .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
  84         .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
  85         .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
  86         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  87 };
  88
  89 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
  90         .sdram_config_init              = 0x61851B32,
  91         .sdram_config                   = 0x61851B32,
  92         .ref_ctrl                       = 0x00001035,
  93         .sdram_tim1                     = 0xCCCF36B3,
  94         .sdram_tim2                     = 0x308F7FDA,
  95         .sdram_tim3                     = 0x027F88A8,
  96         .read_idle_ctrl                 = 0x00050000,
  97         .zq_config                      = 0x0007190B,
  98         .temp_alert_config              = 0x00000000,
  99         .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 100         .emif_ddr_phy_ctlr_1            = 0x0024420A,
 101         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 102         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 103         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 104         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 105         .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 106         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 107         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 108         .emif_rd_wr_lvl_ctl             = 0x00000000,
 109         .emif_rd_wr_exec_thresh         = 0x00000305
 110 };
 111
 112 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 113         .dmm_lisa_map_0 = 0x0,
 114         .dmm_lisa_map_1 = 0x0,
 115         .dmm_lisa_map_2 = 0x80740300,
 116         .dmm_lisa_map_3 = 0xFF020100
 117 };
 118
 119 const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 120         0x01004010,
 121         0x00001004,
 122         0x04010040,
 123         0x01004010,
 124         0x00001004,
 125         0x00000000,
 126         0x00000000,
 127         0x00000000,
 128         0x80080080,
 129         0x00800800,
 130         0x08102040,
 131         0x00000001,
 132         0x540A8150,
 133         0xA81502a0,
 134         0x002A0540,
 135         0x00000000,
 136         0x00000000,
 137         0x00000000,
 138         0x00000077
 139 };
 140
 141 const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 142         0x01004010,
 143         0x00001004,
 144         0x04010040,
 145         0x01004010,
 146         0x00001004,
 147         0x00000000,
 148         0x00000000,
 149         0x00000000,
 150         0x80080080,
 151         0x00800800,
 152         0x08102040,
 153         0x00000002,
 154         0x0,
 155         0x0,
 156         0x0,
 157         0x00000000,
 158         0x00000000,
 159         0x00000000,
 160         0x00000057
 161 };
 162
 163 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 164 {
 165         if (omap_revision() == OMAP5432_ES1_0)
 166                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 167         else
 168                 *regs = &emif_regs_532_mhz_2cs;
 169 }
 170 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 171         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 172
 173 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 174                                                 **dmm_lisa_regs)
 175 {
 176         *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 177 }
 178
 179 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 180         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 181
 182 #else
 183
 184 static const struct lpddr2_device_details dev_4G_S4_details = {
 185         .type           = LPDDR2_TYPE_S4,
 186         .density        = LPDDR2_DENSITY_4Gb,
 187         .io_width       = LPDDR2_IO_WIDTH_32,
 188         .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 189 };
 190
 191 static void emif_get_device_details_sdp(u32 emif_nr,
 192                 struct lpddr2_device_details *cs0_device_details,
 193                 struct lpddr2_device_details *cs1_device_details)
 194 {
 195         /* EMIF1 & EMIF2 have identical configuration */
 196         *cs0_device_details = dev_4G_S4_details;
 197         *cs1_device_details = dev_4G_S4_details;
 198 }
 199
 200 void emif_get_device_details(u32 emif_nr,
 201                 struct lpddr2_device_details *cs0_device_details,
 202                 struct lpddr2_device_details *cs1_device_details)
 203         __attribute__((weak, alias("emif_get_device_details_sdp")));
 204
 205 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 206
 207 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 208 {
 209         u32 *ext_phy_ctrl_base = 0;
 210         u32 *emif_ext_phy_ctrl_base = 0;
 211         u32 i = 0;
 212
 213         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 214
 215         ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 216         emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 217
 218         /* Configure external phy control timing registers */
 219         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 220                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 221                 /* Update shadow registers */
 222                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 223         }
 224
 225         /*
 226          * external phy 6-24 registers do not change with
 227          * ddr frequency
 228          */
 229         for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
 230                 writel(ext_phy_ctrl_const_base[i],
 231                                         emif_ext_phy_ctrl_base++);
 232                 /* Update shadow registers */
 233                 writel(ext_phy_ctrl_const_base[i],
 234                                         emif_ext_phy_ctrl_base++);
 235         }
 236 }
 237
 238 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 239 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 240         .max_freq       = 532000000,
 241         .RL             = 8,
 242         .tRPab          = 21,
 243         .tRCD           = 18,
 244         .tWR            = 15,
 245         .tRASmin        = 42,
 246         .tRRD           = 10,
 247         .tWTRx2         = 15,
 248         .tXSR           = 140,
 249         .tXPx2          = 15,
 250         .tRFCab         = 130,
 251         .tRTPx2         = 15,
 252         .tCKE           = 3,
 253         .tCKESR         = 15,
 254         .tZQCS          = 90,
 255         .tZQCL          = 360,
 256         .tZQINIT        = 1000,
 257         .tDQSCKMAXx2    = 11,
 258         .tRASmax        = 70,
 259         .tFAW           = 50
 260 };
 261
 262 static const struct lpddr2_min_tck min_tck = {
 263         .tRL            = 3,
 264         .tRP_AB         = 3,
 265         .tRCD           = 3,
 266         .tWR            = 3,
 267         .tRAS_MIN       = 3,
 268         .tRRD           = 2,
 269         .tWTR           = 2,
 270         .tXP            = 2,
 271         .tRTP           = 2,
 272         .tCKE           = 3,
 273         .tCKESR         = 3,
 274         .tFAW           = 8
 275 };
 276
 277 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 278         &timings_jedec_532_mhz
 279 };
 280
 281 static const struct lpddr2_device_timings dev_4G_S4_timings = {
 282         .ac_timings     = ac_timings,
 283         .min_tck        = &min_tck,
 284 };
 285
 286 void emif_get_device_timings_sdp(u32 emif_nr,
 287                 const struct lpddr2_device_timings **cs0_device_timings,
 288                 const struct lpddr2_device_timings **cs1_device_timings)
 289 {
 290         /* Identical devices on EMIF1 & EMIF2 */
 291         *cs0_device_timings = &dev_4G_S4_timings;
 292         *cs1_device_timings = &dev_4G_S4_timings;
 293 }
 294
 295 void emif_get_device_timings(u32 emif_nr,
 296                 const struct lpddr2_device_timings **cs0_device_timings,
 297                 const struct lpddr2_device_timings **cs1_device_timings)
 298         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 299
 300 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */