arch/arm/cpu/armv7/socfpga/spl.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/u-boot.h>
  10 #include <asm/utils.h>
  11 #include <image.h>
  12 #include <asm/arch/reset_manager.h>
  13 #include <spl.h>
  14 #include <asm/arch/system_manager.h>
  15 #include <asm/arch/freeze_controller.h>
  16 #include <asm/arch/clock_manager.h>
  17 #include <asm/arch/scan_manager.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #define MAIN_VCO_BASE (                                 \
  22         (CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<             \
  23                 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |   \
  24         (CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<             \
  25                 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)     \
  26         )
  27
  28 #define PERI_VCO_BASE (                                 \
  29         (CONFIG_HPS_PERPLLGRP_VCO_PSRC <<               \
  30                 CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |     \
  31         (CONFIG_HPS_PERPLLGRP_VCO_DENOM <<              \
  32                 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |    \
  33         (CONFIG_HPS_PERPLLGRP_VCO_NUMER <<              \
  34                 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)      \
  35         )
  36
  37 #define SDR_VCO_BASE (                                  \
  38         (CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<               \
  39                 CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |     \
  40         (CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<              \
  41                 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |    \
  42         (CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<              \
  43                 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)      \
  44         )
  45
  46 u32 spl_boot_device(void)
  47 {
  48         return BOOT_DEVICE_RAM;
  49 }
  50
  51 /*
  52  * Board initialization after bss clearance
  53  */
  54 void spl_board_init(void)
  55 {
  56 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  57         cm_config_t cm_default_cfg = {
  58                 /* main group */
  59                 MAIN_VCO_BASE,
  60                 (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
  61                         CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
  62                 (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
  63                         CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
  64                 (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
  65                         CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
  66                 (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
  67                         CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
  68                 (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
  69                         CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
  70                 (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
  71                         CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
  72                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
  73                         CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
  74                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
  75                         CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
  76                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
  77                         CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
  78                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
  79                         CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
  80                 (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
  81                         CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
  82                 (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
  83                         CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
  84                 (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
  85                         CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
  86                 (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
  87                         CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
  88                 (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
  89                         CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
  90
  91                 /* peripheral group */
  92                 PERI_VCO_BASE,
  93                 (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
  94                         CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
  95                 (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
  96                         CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
  97                 (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
  98                         CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
  99                 (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
 100                         CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
 101                 (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
 102                         CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
 103                 (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
 104                         CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
 105                 (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
 106                         CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
 107                 (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
 108                         CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
 109                 (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
 110                         CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
 111                 (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
 112                         CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
 113                 (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
 114                         CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
 115                 (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
 116                         CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
 117                 (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
 118                         CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
 119                 (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
 120                         CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
 121
 122                 /* sdram pll group */
 123                 SDR_VCO_BASE,
 124                 (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
 125                         CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
 126                 (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
 127                         CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
 128                 (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
 129                         CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
 130                 (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
 131                         CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
 132                 (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
 133                         CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
 134                 (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
 135                         CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
 136                 (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
 137                         CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
 138                 (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
 139                         CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
 140
 141         };
 142
 143         debug("Freezing all I/O banks\n");
 144         /* freeze all IO banks */
 145         sys_mgr_frzctrl_freeze_req();
 146
 147         debug("Reconfigure Clock Manager\n");
 148         /* reconfigure the PLLs */
 149         cm_basic_init(&cm_default_cfg);
 150
 151         /* configure the IOCSR / IO buffer settings */
 152         if (scan_mgr_configure_iocsr())
 153                 hang();
 154
 155         /* configure the pin muxing through system manager */
 156         sysmgr_pinmux_init();
 157 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
 158
 159         /* de-assert reset for peripherals and bridges based on handoff */
 160         reset_deassert_peripherals_handoff();
 161
 162         debug("Unfreezing/Thaw all I/O banks\n");
 163         /* unfreeze / thaw all IO banks */
 164         sys_mgr_frzctrl_thaw_req();
 165
 166         /* enable console uart printing */
 167         preloader_console_init();
 168 }