2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm-offsets.h>
35 #include <asm/system.h>
39 ldr pc, _undefined_instruction
40 ldr pc, _software_interrupt
41 ldr pc, _prefetch_abort
46 #ifdef CONFIG_SPL_BUILD
47 _undefined_instruction: .word _undefined_instruction
48 _software_interrupt: .word _software_interrupt
49 _prefetch_abort: .word _prefetch_abort
50 _data_abort: .word _data_abort
51 _not_used: .word _not_used
54 _pad: .word 0x12345678 /* now 16*4=64 */
56 _undefined_instruction: .word undefined_instruction
57 _software_interrupt: .word software_interrupt
58 _prefetch_abort: .word prefetch_abort
59 _data_abort: .word data_abort
60 _not_used: .word not_used
63 _pad: .word 0x12345678 /* now 16*4=64 */
64 #endif /* CONFIG_SPL_BUILD */
69 .balignl 16,0xdeadbeef
70 /*************************************************************************
72 * Startup Code (reset vector)
74 * do important init only if we don't start from memory!
75 * setup Memory and board specific bits prior to relocation.
76 * relocate armboot to ram
79 *************************************************************************/
83 .word CONFIG_SYS_TEXT_BASE
87 * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
88 * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
89 * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
90 * to pick up its reset vector, which points here.
98 * These are defined in the board-specific linker script.
100 .globl _bss_start_ofs
102 .word __bss_start - _start
104 .global _image_copy_end_ofs
106 .word __image_copy_end - _start
110 .word __bss_end__ - _start
116 #ifdef CONFIG_USE_IRQ
117 /* IRQ stack memory (calculated at run-time) */
118 .globl IRQ_STACK_START
122 /* IRQ stack memory (calculated at run-time) */
123 .globl FIQ_STACK_START
128 /* IRQ stack memory (calculated at run-time) + 8 bytes */
129 .globl IRQ_STACK_START_IN
134 * the actual reset code
140 * set the cpu to SVC32 mode
149 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
150 * Continue to use ROM code vector only in OMAP4 spl)
152 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
153 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
154 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
155 bic r0, #CR_V @ V = 0
156 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
158 /* Set vector address in CP15 VBAR register */
160 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
163 #if defined(CONFIG_OMAP34XX)
164 /* Copy vectors to mask ROM indirect addr */
165 adr r0, _start @ r0 <- current position of code
166 add r0, r0, #4 @ skip reset vector
167 mov r2, #64 @ r2 <- size to copy
168 add r2, r0, r2 @ r2 <- source end address
169 mov r1, #SRAM_OFFSET0 @ build vect addr
170 mov r3, #SRAM_OFFSET1
172 mov r3, #SRAM_OFFSET2
175 ldmia r0!, {r3 - r10} @ copy from source address [r0]
176 stmia r1!, {r3 - r10} @ copy to target address [r1]
177 cmp r0, r2 @ until source end address [r2]
178 bne next @ loop until equal */
179 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
180 /* No need to copy/exec the clock code - DPLL adjust already done
181 * in NAND/oneNAND Boot.
183 bl cpy_clk_code @ put dpll adjust code behind vectors
184 #endif /* NAND Boot */
186 /* the mask ROM code should have PLL and others stable */
187 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
191 /* Set stackpointer in internal RAM to call board_init_f */
193 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
194 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
198 /*------------------------------------------------------------------------------*/
201 * void relocate_code (addr_sp, gd, addr_moni)
203 * This "function" does not return, instead it continues in RAM
204 * after relocating the monitor code.
209 mov r4, r0 /* save addr_sp */
210 mov r5, r1 /* save addr of gd */
211 mov r6, r2 /* save addr of destination */
213 /* Set up the stack */
219 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
220 beq clear_bss /* skip relocation */
221 mov r1, r6 /* r1 <- scratch for copy_loop */
222 ldr r3, _image_copy_end_ofs
223 add r2, r0, r3 /* r2 <- source end address */
226 ldmia r0!, {r9-r10} /* copy from source address [r0] */
227 stmia r1!, {r9-r10} /* copy to target address [r1] */
228 cmp r0, r2 /* until source end address [r2] */
231 #ifndef CONFIG_SPL_BUILD
233 * fix .rel.dyn relocations
235 ldr r0, _TEXT_BASE /* r0 <- Text base */
236 sub r9, r6, r0 /* r9 <- relocation offset */
237 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
238 add r10, r10, r0 /* r10 <- sym table in FLASH */
239 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
240 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
241 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
242 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
244 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
245 add r0, r0, r9 /* r0 <- location to fix up in RAM */
248 cmp r7, #23 /* relative fixup? */
250 cmp r7, #2 /* absolute fixup? */
252 /* ignore unknown type of fixup */
255 /* absolute fix: set location to (offset) symbol value */
256 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
257 add r1, r10, r1 /* r1 <- address of symbol in table */
258 ldr r1, [r1, #4] /* r1 <- symbol value */
259 add r1, r1, r9 /* r1 <- relocated sym addr */
262 /* relative fix: increase location by offset */
267 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
272 .word __rel_dyn_start - _start
274 .word __rel_dyn_end - _start
276 .word __dynsym_start - _start
278 #endif /* #ifndef CONFIG_SPL_BUILD */
281 #ifdef CONFIG_SPL_BUILD
282 /* No relocation for SPL */
286 ldr r0, _bss_start_ofs
288 mov r4, r6 /* reloc addr */
292 mov r2, #0x00000000 /* clear */
294 clbss_l:str r2, [r0] /* clear loop... */
300 * We are done. Do not return, instead branch to second part of board
301 * initialization, now running from RAM.
305 * If I-cache is enabled invalidate it
307 #ifndef CONFIG_SYS_ICACHE_OFF
308 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
309 mcr p15, 0, r0, c7, c10, 4 @ DSB
310 mcr p15, 0, r0, c7, c5, 4 @ ISB
312 ldr r0, _board_init_r_ofs
316 /* setup parameters for board_init_r */
317 mov r0, r5 /* gd_t */
318 mov r1, r6 /* dest_addr */
323 .word board_init_r - _start
326 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
327 /*************************************************************************
329 * CPU_init_critical registers
331 * setup important registers
332 * setup memory timing
334 *************************************************************************/
339 mov r0, #0 @ set up for MCR
340 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
341 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
342 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
343 mcr p15, 0, r0, c7, c10, 4 @ DSB
344 mcr p15, 0, r0, c7, c5, 4 @ ISB
347 * disable MMU stuff and caches
349 mrc p15, 0, r0, c1, c0, 0
350 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
351 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
352 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
353 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
354 #ifdef CONFIG_SYS_ICACHE_OFF
355 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
357 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
359 mcr p15, 0, r0, c1, c0, 0
362 * Jump to board specific initialization...
363 * The Mask ROM will have already initialized
364 * basic memory. Go here to bump up clock rate and handle
365 * wake up conditions.
367 mov ip, lr @ persevere link reg across call
368 bl lowlevel_init @ go setup pll,mux,memory
369 mov lr, ip @ restore link
370 mov pc, lr @ back to my caller
373 #ifndef CONFIG_SPL_BUILD
375 *************************************************************************
379 *************************************************************************
384 #define S_FRAME_SIZE 72
406 #define MODE_SVC 0x13
410 * use bad_save_user_regs for abort/prefetch/undef/swi ...
411 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
414 .macro bad_save_user_regs
415 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
417 stmia sp, {r0 - r12} @ Save user registers (now in
419 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
421 ldmia r2, {r2 - r3} @ get values for "aborted" pc
422 @ and cpsr (into parm regs)
423 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
427 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
428 mov r0, sp @ save current stack into r0
432 .macro irq_save_user_regs
433 sub sp, sp, #S_FRAME_SIZE
434 stmia sp, {r0 - r12} @ Calling r0-r12
435 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
436 @ a reserved stack spot would
438 stmdb r8, {sp, lr}^ @ Calling SP, LR
439 str lr, [r8, #0] @ Save calling PC
441 str r6, [r8, #4] @ Save CPSR
442 str r0, [r8, #8] @ Save OLD_R0
446 .macro irq_restore_user_regs
447 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
449 ldr lr, [sp, #S_PC] @ Get PC
450 add sp, sp, #S_FRAME_SIZE
451 subs pc, lr, #4 @ return & move spsr_svc into
456 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
459 str lr, [r13] @ save caller lr in position 0
461 mrs lr, spsr @ get the spsr
462 str lr, [r13, #4] @ save spsr in position 1 of
465 mov r13, #MODE_SVC @ prepare SVC-Mode
467 msr spsr, r13 @ switch modes, make sure
469 mov lr, pc @ capture return pc
470 movs pc, lr @ jump to next instruction &
474 .macro get_bad_stack_swi
475 sub r13, r13, #4 @ space on current stack for
477 str r0, [r13] @ save R0's value.
478 ldr r0, IRQ_STACK_START_IN @ get data regions start
479 @ spots for abort stack
480 str lr, [r0] @ save caller lr in position 0
482 mrs r0, spsr @ get the spsr
483 str lr, [r0, #4] @ save spsr in position 1 of
485 ldr r0, [r13] @ restore r0
486 add r13, r13, #4 @ pop stack entry
489 .macro get_irq_stack @ setup IRQ stack
490 ldr sp, IRQ_STACK_START
493 .macro get_fiq_stack @ setup FIQ stack
494 ldr sp, FIQ_STACK_START
501 undefined_instruction:
504 bl do_undefined_instruction
510 bl do_software_interrupt
530 #ifdef CONFIG_USE_IRQ
537 irq_restore_user_regs
542 /* someone ought to write a more effective fiq_save_user_regs */
545 irq_restore_user_regs
561 #endif /* CONFIG_USE_IRQ */
562 #endif /* CONFIG_SPL_BUILD */