3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
11 #include <linux/linkage.h>
12 #include <asm/macro.h>
13 #include <asm/armv8/mmu.h>
15 /*************************************************************************
17 * Startup Code (reset vector)
19 *************************************************************************/
29 .quad CONFIG_SYS_TEXT_BASE
32 * These are defined in the linker script.
40 .quad __bss_start - _start
44 .quad __bss_end - _start
48 * Could be EL3/EL2/EL1, Initial State:
49 * Little Endian, MMU Disabled, i/dCache Disabled
52 switch_el x1, 3f, 2f, 1f
55 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
57 msr cptr_el3, xzr /* Enable FP/SIMD */
58 ldr x0, =COUNTER_FREQUENCY
59 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
63 msr cptr_el2, x0 /* Enable FP/SIMD */
67 msr cpacr_el1, x0 /* Enable FP/SIMD */
70 /* Apply ARM core specific erratas */
74 * Cache/BPB/TLB Invalidate
75 * i-cache is invalidated before enabled in icache_enable()
76 * tlb is invalidated before mmu is enabled in dcache_enable()
77 * d-cache is invalidated before enabled in dcache_enable()
80 /* Processor specific initialization */
83 #ifdef CONFIG_ARMV8_MULTIENTRY
84 branch_if_master x0, x1, master_cpu
91 ldr x1, =CPU_RELEASE_ADDR
94 br x0 /* branch to the given address */
96 /* On the master CPU */
97 #endif /* CONFIG_ARMV8_MULTIENTRY */
101 /*-----------------------------------------------------------------------*/
103 WEAK(apply_core_errata)
105 mov x29, lr /* Save LR */
106 /* For now, we support Cortex-A57 specific errata only */
108 /* Check if we are running on a Cortex-A57 core */
109 branch_if_a57_core x0, apply_a57_core_errata
111 mov lr, x29 /* Restore LR */
114 apply_a57_core_errata:
116 #ifdef CONFIG_ARM_ERRATA_828024
117 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
118 /* Disable non-allocate hint of w-b-n-a memory type */
120 /* Disable write streaming no L1-allocate threshold */
122 /* Disable write streaming no-allocate threshold */
124 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
127 #ifdef CONFIG_ARM_ERRATA_826974
128 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
129 /* Disable speculative load execution ahead of a DMB */
131 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
134 #ifdef CONFIG_ARM_ERRATA_833069
135 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
136 /* Disable Enable Invalidates of BTB bit */
138 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
141 ENDPROC(apply_core_errata)
143 /*-----------------------------------------------------------------------*/
146 mov x29, lr /* Save LR */
148 #ifndef CONFIG_ARMV8_MULTIENTRY
150 * For single-entry systems the lowlevel init is very simple.
155 #else /* CONFIG_ARMV8_MULTIENTRY is set */
157 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
158 branch_if_slave x0, 1f
162 #if defined(CONFIG_GICV3)
164 bl gic_init_secure_percpu
165 #elif defined(CONFIG_GICV2)
168 bl gic_init_secure_percpu
172 branch_if_master x0, x1, 2f
175 * Slave should wait for master clearing spin table.
176 * This sync prevent salves observing incorrect
177 * value of spin table and jumping to wrong place.
179 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
183 bl gic_wait_for_interrupt
187 * All slaves will enter EL2 and optionally EL1.
189 bl armv8_switch_to_el2
190 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
191 bl armv8_switch_to_el1
194 #endif /* CONFIG_ARMV8_MULTIENTRY */
197 mov lr, x29 /* Restore LR */
199 ENDPROC(lowlevel_init)
201 WEAK(smp_kick_all_cpus)
202 /* Kick secondary cpus up by SGI 0 interrupt */
203 mov x29, lr /* Save LR */
204 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
206 bl gic_kick_secondary_cpus
208 mov lr, x29 /* Restore LR */
210 ENDPROC(smp_kick_all_cpus)
212 /*-----------------------------------------------------------------------*/
214 ENTRY(c_runtime_cpu_setup)
217 switch_el x1, 3f, 2f, 1f
226 ENDPROC(c_runtime_cpu_setup)