3 * Copyright 2013 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
11 /include/ "imx6qdl.dtsi"
19 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
29 clock-latency = <61036>; /* two CLK32 periods */
30 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
31 <&clks 17>, <&clks 170>;
32 clock-names = "arm", "pll2_pfd2_396m", "step",
33 "pll1_sw", "pll1_sys";
34 arm-supply = <®_arm>;
35 pu-supply = <®_pu>;
36 soc-supply = <®_soc>;
40 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
46 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
52 compatible = "arm,cortex-a9";
54 next-level-cache = <&L2>;
59 aips-bus@02000000 { /* AIPS1 */
61 ecspi5: ecspi@02018000 {
64 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
65 reg = <0x02018000 0x4000>;
66 interrupts = <0 35 0x04>;
67 clocks = <&clks 116>, <&clks 116>;
68 clock-names = "ipg", "per";
73 iomuxc: iomuxc@020e0000 {
74 compatible = "fsl,imx6q-iomuxc";
75 reg = <0x020e0000 0x4000>;
77 /* shared pinctrl settings */
79 pinctrl_audmux_1: audmux-1 {
81 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
82 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
83 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
84 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
90 pinctrl_ecspi1_1: ecspi1grp-1 {
92 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
93 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
94 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
100 pinctrl_enet_1: enetgrp-1 {
102 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
103 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
104 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
105 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
106 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
107 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
108 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
109 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
110 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
111 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
112 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
113 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
114 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
115 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
116 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
117 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
121 pinctrl_enet_2: enetgrp-2 {
123 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
124 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
125 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
126 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
127 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
128 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
129 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
130 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
131 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
132 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
133 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
134 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
135 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
136 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
137 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
143 pinctrl_gpmi_nand_1: gpmi-nand-1 {
145 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
146 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
147 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
148 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
149 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
150 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
151 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
152 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
153 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
154 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
155 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
156 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
157 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
158 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
159 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
160 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
161 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
162 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
163 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
169 pinctrl_i2c1_1: i2c1grp-1 {
171 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
172 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
178 pinctrl_uart1_1: uart1grp-1 {
180 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
181 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
184 pinctrl_uart1_2: uart1-grp-2 {
186 120 0x1b0b1 /* MX6Q_PAD_EIM_D19__UART1_CTS */
187 128 0x1b0b1 /* MX6Q_PAD_EIM_D20__UART1_RTS */
191 pinctrl_uart1_3: uart1grp-3 {
193 1242 0x1b0b1 /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
194 1250 0x1b0b1 /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
197 pinctrl_uart1_4: uart1-grp-4 {
199 1290 0x1b0b1 /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
200 1298 0x1b0b1 /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
206 pinctrl_uart2_1: uart2grp-1 {
208 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
209 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
212 pinctrl_uart2_2: uart2grp-2 {
214 199 0x1b0b1 /* MX6Q_PAD_EIM_D28__UART2_CTS */
215 206 0x1b0b1 /* MX6Q_PAD_EIM_D29__UART2_RTS */
219 pinctrl_uart2_3: uart2grp-3 {
221 1258 0x1b0b1 /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
222 1266 0x1b0b1 /* MX6Q_PAD_SD3_DAT6__UART2_RXD */
225 pinctrl_uart2_4: uart2grp-4 {
227 1274 0x1b0b1 /* MX6Q_PAD_SD3_CMD__UART2_CTS */
228 1282 0x1b0b1 /* MX6Q_PAD_SD3_CLK__UART2_RTS */
232 pinctrl_uart2_5: uart2grp-5 {
234 1518 0x1b0b1 /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
235 1494 0x1b0b1 /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
238 pinctrl_uart2_6: uart2grp-6 {
240 1510 0x1b0b1 /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
241 1502 0x1b0b1 /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
245 pinctrl_uart2_7: uart2grp-7 {
247 1019 0x1b0b1 /* MX6Q_PAD_GPIO_7__UART2_TXD */
248 1027 0x1b0b1 /* MX6Q_PAD_GPIO_8__UART2_RXD */
254 pinctrl_uart3_1: uart3grp-1 {
256 165 0x1b0b1 /* MX6Q_PAD_EIM_D24__UART3_TXD */
257 173 0x1b0b1 /* MX6Q_PAD_EIM_D25__UART3_RXD */
260 pinctrl_uart3_2: uart3grp-2 {
262 149 0x1b0b1 /* MX6Q_PAD_EIM_D23__UART3_CTS */
263 157 0x1b0b1 /* MX6Q_PAD_EIM_EB3__UART3_RTS */
267 pinctrl_uart3_3: uart3grp-3 {
269 1388 0x1b0b1 /* MX6Q_PAD_SD4_CMD__UART3_TXD */
270 1394 0x1b0b1 /* MX6Q_PAD_SD4_CLK__UART3_RXD */
273 pinctrl_uart3_4: uart3grp-4 {
275 1313 0x1b0b1 /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
276 1321 0x1b0b1 /* MX6Q_PAD_SD3_RST__UART3_RTS */
280 pinctrl_uart3_5: uart3grp-5 {
282 214 0x1b0b1 /* MX6Q_PAD_EIM_D30__UART3_CTS */
283 222 0x1b0b1 /* MX6Q_PAD_EIM_D31__UART3_RTS */
289 pinctrl_uart4_1: uart4grp-1 {
291 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
292 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
298 pinctrl_usbotg_1: usbotggrp-1 {
300 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
306 pinctrl_usdhc1_1: usdhc1grp-1 {
308 1548 0x17059 /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
309 1562 0x10059 /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
310 1532 0x17059 /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
311 1524 0x17059 /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
312 1554 0x17059 /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
313 1540 0x17059 /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
314 1398 0x17059 /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
315 1406 0x17059 /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
316 1414 0x17059 /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
317 1422 0x17059 /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
321 pinctrl_usdhc1_2: usdhc1grp-2 {
323 1548 0x17059 /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
324 1562 0x10059 /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
325 1532 0x17059 /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
326 1524 0x17059 /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
327 1554 0x17059 /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
328 1540 0x17059 /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
334 pinctrl_usdhc2_1: usdhc2grp-1 {
336 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
337 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
338 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
339 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
340 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
341 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
342 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
343 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
344 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
345 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
349 pinctrl_usdhc2_2: usdhc2grp-2 {
351 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
352 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
353 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
354 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
355 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
356 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
362 pinctrl_usdhc3_1: usdhc3grp-1 {
364 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
365 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
366 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
367 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
368 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
369 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
370 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
371 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
372 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
373 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
377 pinctrl_usdhc3_2: usdhc3grp-2 {
379 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
380 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
381 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
382 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
383 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
384 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
390 pinctrl_usdhc4_1: usdhc4grp-1 {
392 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
393 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
394 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
395 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
396 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
397 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
398 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
399 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
400 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
401 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
405 pinctrl_usdhc4_2: usdhc4grp-2 {
407 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
408 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
409 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
410 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
411 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
412 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
421 compatible = "fsl,imx6q-ipu";
422 reg = <0x02800000 0x400000>;
423 interrupts = <0 8 0x4 0 7 0x4>;
424 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
425 clock-names = "bus", "di0", "di1";