arch/arm/dts/socfpga_arria5_socdk.dts

   1 /*
   2  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include "socfpga_arria5.dtsi"
   8
   9 / {
  10         model = "Altera SOCFPGA Arria V SoC Development Kit";
  11         compatible = "altr,socfpga-arria5", "altr,socfpga";
  12
  13         chosen {
  14                 bootargs = "console=ttyS0,115200";
  15         };
  16
  17         memory {
  18                 name = "memory";
  19                 device_type = "memory";
  20                 reg = <0x0 0x40000000>; /* 1GB */
  21         };
  22
  23         aliases {
  24                 /* this allow the ethaddr uboot environmnet variable contents
  25                  * to be added to the gmac1 device tree blob.
  26                  */
  27                 ethernet0 = &gmac1;
  28         };
  29
  30         regulator_3_3v: 3-3-v-regulator {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "3.3V";
  33                 regulator-min-microvolt = <3300000>;
  34                 regulator-max-microvolt = <3300000>;
  35         };
  36 };
  37
  38 &gmac1 {
  39         status = "okay";
  40         phy-mode = "rgmii";
  41
  42         rxd0-skew-ps = <0>;
  43         rxd1-skew-ps = <0>;
  44         rxd2-skew-ps = <0>;
  45         rxd3-skew-ps = <0>;
  46         txen-skew-ps = <0>;
  47         txc-skew-ps = <2600>;
  48         rxdv-skew-ps = <0>;
  49         rxc-skew-ps = <2000>;
  50 };
  51
  52 &i2c0 {
  53         status = "okay";
  54
  55         eeprom@51 {
  56                 compatible = "atmel,24c32";
  57                 reg = <0x51>;
  58                 pagesize = <32>;
  59         };
  60
  61         rtc@68 {
  62                 compatible = "dallas,ds1339";
  63                 reg = <0x68>;
  64         };
  65 };
  66
  67 &mmc0 {
  68         vmmc-supply = <&regulator_3_3v>;
  69         vqmmc-supply = <&regulator_3_3v>;
  70 };
  71
  72 &usb1 {
  73         status = "okay";
  74 };
  75
  76 &qspi {
  77         status = "okay";
  78
  79         flash0: n25q00@0 {
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 compatible = "n25q00";
  83                 reg = <0>;      /* chip select */
  84                 spi-max-frequency = <50000000>;
  85                 m25p,fast-read;
  86                 page-size = <256>;
  87                 block-size = <16>; /* 2^16, 64KB */
  88                 read-delay = <4>;  /* delay value in read data capture register */
  89                 tshsl-ns = <50>;
  90                 tsd2d-ns = <50>;
  91                 tchsh-ns = <4>;
  92                 tslch-ns = <4>;
  93         };
  94 };