2 * Based on the iomux-v3.c from Linux kernel:
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
7 * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
14 #if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
15 #include <asm/arch/sys_proto.h>
17 #include <asm/imx-common/iomux-v3.h>
19 static void *base = (void *)IOMUXC_BASE_ADDR;
22 * configures a single pad in the iomuxer
24 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
26 u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
27 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
29 (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
31 (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
33 (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
34 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
36 #if defined CONFIG_MX6SL
37 /* Check whether LVE bit needs to be set */
38 if (pad_ctrl & PAD_CTL_LVE) {
39 pad_ctrl &= ~PAD_CTL_LVE;
40 pad_ctrl |= PAD_CTL_LVE_BIT;
44 printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n",
45 i, pad, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl,
46 pad & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input);
50 __raw_writel(mux_mode, base + mux_ctrl_ofs);
53 __raw_writel(sel_input, base + sel_input_ofs);
55 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
56 if (pad & PAD_CTRL_VALID)
57 __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
60 if ((pad & PAD_CTRL_VALID) && pad_ctrl_ofs)
61 __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
65 /* configures a list of pads within declared with IOMUX_PADS macro */
66 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
69 iomux_v3_cfg_t const *p = pad_list;
73 #if defined(CONFIG_MX6QDL)
75 if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
80 for (i = 0; i < count; i++) {
81 imx_iomux_v3_setup_pad(*p);
86 void imx_iomux_set_gpr_register(int group, int start_bit,
87 int num_bits, int value)
89 u32 reg = readl(base + group * 4);
91 reg &= ~(((1 << num_bits) - 1) << start_bit);
92 reg |= value << start_bit;
93 writel(reg, base + group * 4);