6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/hardware.h>
17 /* AM335X EMIF Register values */
18 #define VTP_CTRL_READY (0x1 << 5)
19 #define VTP_CTRL_ENABLE (0x1 << 6)
20 #define VTP_CTRL_START_EN (0x1)
22 #define DDR_CKE_CTRL_NORMAL 0x3
24 #define DDR_CKE_CTRL_NORMAL 0x1
26 #define PHY_EN_DYN_PWRDN (0x1 << 20)
28 /* Micron MT47H128M16RT-25E */
29 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
30 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
31 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
32 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
33 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
34 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
35 #define MT47H128M16RT25E_RATIO 0x80
36 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00
37 #define MT47H128M16RT25E_RD_DQS 0x12
38 #define MT47H128M16RT25E_WR_DQS 0x00
39 #define MT47H128M16RT25E_PHY_WRLVL 0x00
40 #define MT47H128M16RT25E_PHY_GATELVL 0x00
41 #define MT47H128M16RT25E_PHY_WR_DATA 0x40
42 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80
43 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
45 /* Micron MT41J128M16JT-125 */
46 #define MT41J128MJT125_EMIF_READ_LATENCY 0x06
47 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B
48 #define MT41J128MJT125_EMIF_TIM2 0x26337FDA
49 #define MT41J128MJT125_EMIF_TIM3 0x501F830F
50 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
51 #define MT41J128MJT125_EMIF_SDREF 0x0000093B
52 #define MT41J128MJT125_ZQ_CFG 0x50074BE4
53 #define MT41J128MJT125_RATIO 0x40
54 #define MT41J128MJT125_INVERT_CLKOUT 0x1
55 #define MT41J128MJT125_RD_DQS 0x3B
56 #define MT41J128MJT125_WR_DQS 0x85
57 #define MT41J128MJT125_PHY_WR_DATA 0xC1
58 #define MT41J128MJT125_PHY_FIFO_WE 0x100
59 #define MT41J128MJT125_IOCTRL_VALUE 0x18B
61 /* Micron MT41J64M16JT-125 */
62 #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
64 /* Micron MT41J256M16JT-125 */
65 #define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
67 /* Micron MT41J256M8HX-15E */
68 #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
69 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
70 #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
71 #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
72 #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
73 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
74 #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
75 #define MT41J256M8HX15E_RATIO 0x40
76 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1
77 #define MT41J256M8HX15E_RD_DQS 0x3B
78 #define MT41J256M8HX15E_WR_DQS 0x85
79 #define MT41J256M8HX15E_PHY_WR_DATA 0xC1
80 #define MT41J256M8HX15E_PHY_FIFO_WE 0x100
81 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
83 /* Micron MT41K256M16HA-125E */
84 #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
85 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
86 #define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
87 #define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
88 #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
89 #define MT41K256M16HA125E_EMIF_SDREF 0xC30
90 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
91 #define MT41K256M16HA125E_RATIO 0x80
92 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0
93 #define MT41K256M16HA125E_RD_DQS 0x38
94 #define MT41K256M16HA125E_WR_DQS 0x44
95 #define MT41K256M16HA125E_PHY_WR_DATA 0x7D
96 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94
97 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
99 /* Micron MT41J512M8RH-125 on EVM v1.5 */
100 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
101 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
102 #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
103 #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
104 #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
105 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B
106 #define MT41J512M8RH125_ZQ_CFG 0x50074BE4
107 #define MT41J512M8RH125_RATIO 0x80
108 #define MT41J512M8RH125_INVERT_CLKOUT 0x0
109 #define MT41J512M8RH125_RD_DQS 0x3B
110 #define MT41J512M8RH125_WR_DQS 0x3C
111 #define MT41J512M8RH125_PHY_FIFO_WE 0xA5
112 #define MT41J512M8RH125_PHY_WR_DATA 0x74
113 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B
115 /* Samsung K4B2G1646E-BIH9 */
116 #define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07
117 #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
118 #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
119 #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
120 #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
121 #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
122 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
123 #define K4B2G1646EBIH9_RATIO 0x80
124 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
125 #define K4B2G1646EBIH9_RD_DQS 0x35
126 #define K4B2G1646EBIH9_WR_DQS 0x3A
127 #define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
128 #define K4B2G1646EBIH9_PHY_WR_DATA 0x76
129 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
131 #define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
132 #define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
133 #define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
134 #define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
135 #define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
136 #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
137 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
142 void config_dmm(const struct dmm_lisa_map_regs *regs);
147 void config_sdram(const struct emif_regs *regs, int nr);
148 void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
153 void set_sdram_timings(const struct emif_regs *regs, int nr);
158 void config_ddr_phy(const struct emif_regs *regs, int nr);
160 struct ddr_cmd_regs {
161 unsigned int resv0[7];
162 unsigned int cm0csratio; /* offset 0x01C */
163 unsigned int resv1[3];
164 unsigned int cm0iclkout; /* offset 0x02C */
165 unsigned int resv2[8];
166 unsigned int cm1csratio; /* offset 0x050 */
167 unsigned int resv3[3];
168 unsigned int cm1iclkout; /* offset 0x060 */
169 unsigned int resv4[8];
170 unsigned int cm2csratio; /* offset 0x084 */
171 unsigned int resv5[3];
172 unsigned int cm2iclkout; /* offset 0x094 */
173 unsigned int resv6[3];
176 struct ddr_data_regs {
177 unsigned int dt0rdsratio0; /* offset 0x0C8 */
178 unsigned int resv1[4];
179 unsigned int dt0wdsratio0; /* offset 0x0DC */
180 unsigned int resv2[4];
181 unsigned int dt0wiratio0; /* offset 0x0F0 */
183 unsigned int dt0wimode0; /* offset 0x0F8 */
184 unsigned int dt0giratio0; /* offset 0x0FC */
186 unsigned int dt0gimode0; /* offset 0x104 */
187 unsigned int dt0fwsratio0; /* offset 0x108 */
188 unsigned int resv5[4];
189 unsigned int dt0dqoffset; /* offset 0x11C */
190 unsigned int dt0wrsratio0; /* offset 0x120 */
191 unsigned int resv6[4];
192 unsigned int dt0rdelays0; /* offset 0x134 */
193 unsigned int dt0dldiff0; /* offset 0x138 */
194 unsigned int resv7[12];
198 * This structure represents the DDR registers on AM33XX devices.
199 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
200 * correspond to DATA1 registers defined here.
203 unsigned int resv0[3];
204 unsigned int cm0config; /* offset 0x00C */
205 unsigned int cm0configclk; /* offset 0x010 */
206 unsigned int resv1[2];
207 unsigned int cm0csratio; /* offset 0x01C */
208 unsigned int resv2[3];
209 unsigned int cm0iclkout; /* offset 0x02C */
210 unsigned int resv3[4];
211 unsigned int cm1config; /* offset 0x040 */
212 unsigned int cm1configclk; /* offset 0x044 */
213 unsigned int resv4[2];
214 unsigned int cm1csratio; /* offset 0x050 */
215 unsigned int resv5[3];
216 unsigned int cm1iclkout; /* offset 0x060 */
217 unsigned int resv6[4];
218 unsigned int cm2config; /* offset 0x074 */
219 unsigned int cm2configclk; /* offset 0x078 */
220 unsigned int resv7[2];
221 unsigned int cm2csratio; /* offset 0x084 */
222 unsigned int resv8[3];
223 unsigned int cm2iclkout; /* offset 0x094 */
224 unsigned int resv9[12];
225 unsigned int dt0rdsratio0; /* offset 0x0C8 */
226 unsigned int resv10[4];
227 unsigned int dt0wdsratio0; /* offset 0x0DC */
228 unsigned int resv11[4];
229 unsigned int dt0wiratio0; /* offset 0x0F0 */
231 unsigned int dt0wimode0; /* offset 0x0F8 */
232 unsigned int dt0giratio0; /* offset 0x0FC */
234 unsigned int dt0gimode0; /* offset 0x104 */
235 unsigned int dt0fwsratio0; /* offset 0x108 */
236 unsigned int resv14[4];
237 unsigned int dt0dqoffset; /* offset 0x11C */
238 unsigned int dt0wrsratio0; /* offset 0x120 */
239 unsigned int resv15[4];
240 unsigned int dt0rdelays0; /* offset 0x134 */
241 unsigned int dt0dldiff0; /* offset 0x138 */
245 * Encapsulates DDR CMD control registers.
248 unsigned long cmd0csratio;
249 unsigned long cmd0csforce;
250 unsigned long cmd0csdelay;
251 unsigned long cmd0iclkout;
252 unsigned long cmd1csratio;
253 unsigned long cmd1csforce;
254 unsigned long cmd1csdelay;
255 unsigned long cmd1iclkout;
256 unsigned long cmd2csratio;
257 unsigned long cmd2csforce;
258 unsigned long cmd2csdelay;
259 unsigned long cmd2iclkout;
263 * Encapsulates DDR DATA registers.
266 unsigned long datardsratio0;
267 unsigned long datawdsratio0;
268 unsigned long datawiratio0;
269 unsigned long datagiratio0;
270 unsigned long datafwsratio0;
271 unsigned long datawrsratio0;
275 * Configure DDR CMD control registers
277 void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
280 * Configure DDR DATA registers
282 void config_ddr_data(const struct ddr_data *data, int nr);
285 * This structure represents the DDR io control on AM33XX devices.
287 struct ddr_cmdtctrl {
288 unsigned int cm0ioctl;
289 unsigned int cm1ioctl;
290 unsigned int cm2ioctl;
291 unsigned int resv2[12];
292 unsigned int dt0ioctl;
293 unsigned int dt1ioctl;
294 unsigned int dt2ioctrl;
295 unsigned int dt3ioctrl;
296 unsigned int resv3[4];
297 unsigned int emif_sdram_config_ext;
301 unsigned int cm0ioctl;
302 unsigned int cm1ioctl;
303 unsigned int cm2ioctl;
304 unsigned int dt0ioctl;
305 unsigned int dt1ioctl;
306 unsigned int dt2ioctrl;
307 unsigned int dt3ioctrl;
308 unsigned int emif_sdram_config_ext;
312 * Configure DDR io control registers
314 void config_io_ctrl(const struct ctrl_ioregs *ioregs);
317 unsigned int ddrioctrl;
318 unsigned int resv1[325];
319 unsigned int ddrckectrl;
322 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
323 const struct ddr_data *data, const struct cmd_control *ctrl,
324 const struct emif_regs *regs, int nr);
325 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
327 #endif /* _DDR_DEFS_H */