arch/arm/include/asm/arch-armada100/cpu.h

   1 /*
   2  * (C) Copyright 2010
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _ARMADA100CPU_H
  10 #define _ARMADA100CPU_H
  11
  12 #include <asm/io.h>
  13 #include <asm/system.h>
  14
  15 /*
  16  * Main Power Management (MPMU) Registers
  17  * Refer Datasheet Appendix A.8
  18  */
  19 struct armd1mpmu_registers {
  20         u8 pad0[0x08 - 0x00];
  21         u32 fccr;       /*0x0008*/
  22         u32 pocr;       /*0x000c*/
  23         u32 posr;       /*0x0010*/
  24         u32 succr;      /*0x0014*/
  25         u8 pad1[0x030 - 0x014 - 4];
  26         u32 gpcr;       /*0x0030*/
  27         u8 pad2[0x200 - 0x030 - 4];
  28         u32 wdtpcr;     /*0x0200*/
  29         u8 pad3[0x1000 - 0x200 - 4];
  30         u32 apcr;       /*0x1000*/
  31         u32 apsr;       /*0x1004*/
  32         u8 pad4[0x1020 - 0x1004 - 4];
  33         u32 aprr;       /*0x1020*/
  34         u32 acgr;       /*0x1024*/
  35         u32 arsr;       /*0x1028*/
  36 };
  37
  38 /*
  39  * Application Subsystem Power Management
  40  * Refer Datasheet Appendix A.9
  41  */
  42 struct armd1apmu_registers {
  43         u32 pcr;                /* 0x000 */
  44         u32 ccr;                /* 0x004 */
  45         u32 pad1;
  46         u32 ccsr;               /* 0x00C */
  47         u32 fc_timer;           /* 0x010 */
  48         u32 pad2;
  49         u32 ideal_cfg;          /* 0x018 */
  50         u8 pad3[0x04C - 0x018 - 4];
  51         u32 lcdcrc;             /* 0x04C */
  52         u32 cciccrc;            /* 0x050 */
  53         u32 sd1crc;             /* 0x054 */
  54         u32 sd2crc;             /* 0x058 */
  55         u32 usbcrc;             /* 0x05C */
  56         u32 nfccrc;             /* 0x060 */
  57         u32 dmacrc;             /* 0x064 */
  58         u32 pad4;
  59         u32 buscrc;             /* 0x06C */
  60         u8 pad5[0x07C - 0x06C - 4];
  61         u32 wake_clr;           /* 0x07C */
  62         u8 pad6[0x090 - 0x07C - 4];
  63         u32 core_status;        /* 0x090 */
  64         u32 rfsc;               /* 0x094 */
  65         u32 imr;                /* 0x098 */
  66         u32 irwc;               /* 0x09C */
  67         u32 isr;                /* 0x0A0 */
  68         u8 pad7[0x0B0 - 0x0A0 - 4];
  69         u32 mhst;               /* 0x0B0 */
  70         u32 msr;                /* 0x0B4 */
  71         u8 pad8[0x0C0 - 0x0B4 - 4];
  72         u32 msst;               /* 0x0C0 */
  73         u32 pllss;              /* 0x0C4 */
  74         u32 smb;                /* 0x0C8 */
  75         u32 gccrc;              /* 0x0CC */
  76         u8 pad9[0x0D4 - 0x0CC - 4];
  77         u32 smccrc;             /* 0x0D4 */
  78         u32 pad10;
  79         u32 xdcrc;              /* 0x0DC */
  80         u32 sd3crc;             /* 0x0E0 */
  81         u32 sd4crc;             /* 0x0E4 */
  82         u8 pad11[0x0F0 - 0x0E4 - 4];
  83         u32 cfcrc;              /* 0x0F0 */
  84         u32 mspcrc;             /* 0x0F4 */
  85         u32 cmucrc;             /* 0x0F8 */
  86         u32 fecrc;              /* 0x0FC */
  87         u32 pciecrc;            /* 0x100 */
  88         u32 epdcrc;             /* 0x104 */
  89 };
  90
  91 /*
  92  * APB1 Clock Reset/Control Registers
  93  * Refer Datasheet Appendix A.10
  94  */
  95 struct armd1apb1_registers {
  96         u32 uart1;      /*0x000*/
  97         u32 uart2;      /*0x004*/
  98         u32 gpio;       /*0x008*/
  99         u32 pwm1;       /*0x00c*/
 100         u32 pwm2;       /*0x010*/
 101         u32 pwm3;       /*0x014*/
 102         u32 pwm4;       /*0x018*/
 103         u8 pad0[0x028 - 0x018 - 4];
 104         u32 rtc;        /*0x028*/
 105         u32 twsi0;      /*0x02c*/
 106         u32 kpc;        /*0x030*/
 107         u32 timers;     /*0x034*/
 108         u8 pad1[0x03c - 0x034 - 4];
 109         u32 aib;        /*0x03c*/
 110         u32 sw_jtag;    /*0x040*/
 111         u32 timer1;     /*0x044*/
 112         u32 onewire;    /*0x048*/
 113         u8 pad2[0x050 - 0x048 - 4];
 114         u32 asfar;      /*0x050 AIB Secure First Access Reg*/
 115         u32 assar;      /*0x054 AIB Secure Second Access Reg*/
 116         u8 pad3[0x06c - 0x054 - 4];
 117         u32 twsi1;      /*0x06c*/
 118         u32 uart3;      /*0x070*/
 119         u8 pad4[0x07c - 0x070 - 4];
 120         u32 timer2;     /*0x07C*/
 121         u8 pad5[0x084 - 0x07c - 4];
 122         u32 ac97;       /*0x084*/
 123 };
 124
 125 /*
 126 * APB2 Clock Reset/Control Registers
 127 * Refer Datasheet Appendix A.11
 128 */
 129 struct armd1apb2_registers {
 130         u32 pad1[0x01C - 0x000];
 131         u32 ssp1_clkrst;                /* 0x01C */
 132         u32 ssp2_clkrst;                /* 0x020 */
 133         u32 pad2[0x04C - 0x020 - 4];
 134         u32 ssp3_clkrst;                /* 0x04C */
 135         u32 pad3[0x058 - 0x04C - 4];
 136         u32 ssp4_clkrst;                /* 0x058 */
 137         u32 ssp5_clkrst;                /* 0x05C */
 138 };
 139
 140 /*
 141  * CPU Interface Registers
 142  * Refer Datasheet Appendix A.2
 143  */
 144 struct armd1cpu_registers {
 145         u32 chip_id;            /* Chip Id Reg */
 146         u32 pad;
 147         u32 cpu_conf;           /* CPU Conf Reg */
 148         u32 pad1;
 149         u32 cpu_sram_spd;       /* CPU SRAM Speed Reg */
 150         u32 pad2;
 151         u32 cpu_l2c_spd;        /* CPU L2cache Speed Conf */
 152         u32 mcb_conf;           /* MCB Conf Reg */
 153         u32 sys_boot_ctl;       /* Sytem Boot Control */
 154 };
 155
 156 /*
 157  * Functions
 158  */
 159 u32 armd1_sdram_base(int);
 160 u32 armd1_sdram_size(int);
 161
 162 #endif /* _ARMADA100CPU_H */