arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h

   1 /*
   2  * LayerScape Internal Memory Map
   3  *
   4  * Copyright 2014 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H
  10 #define __ARCH_FSL_LSCH3_IMMAP_H_
  11
  12 /* This is chassis generation 3 */
  13
  14 struct sys_info {
  15         unsigned long freq_processor[CONFIG_MAX_CPUS];
  16         unsigned long freq_systembus;
  17         unsigned long freq_ddrbus;
  18         unsigned long freq_ddrbus2;
  19         unsigned long freq_localbus;
  20         unsigned long freq_qe;
  21 #ifdef CONFIG_SYS_DPAA_FMAN
  22         unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
  23 #endif
  24 #ifdef CONFIG_SYS_DPAA_QBMAN
  25         unsigned long freq_qman;
  26 #endif
  27 #ifdef CONFIG_SYS_DPAA_PME
  28         unsigned long freq_pme;
  29 #endif
  30 };
  31
  32 /* Global Utilities Block */
  33 struct ccsr_gur {
  34         u32     porsr1;         /* POR status 1 */
  35         u32     porsr2;         /* POR status 2 */
  36         u8      res_008[0x20-0x8];
  37         u32     gpporcr1;       /* General-purpose POR configuration */
  38         u32     gpporcr2;       /* General-purpose POR configuration 2 */
  39         u32     dcfg_fusesr;    /* Fuse status register */
  40         u32     gpporcr3;
  41         u32     gpporcr4;
  42         u8      res_034[0x70-0x34];
  43         u32     devdisr;        /* Device disable control */
  44         u32     devdisr2;       /* Device disable control 2 */
  45         u32     devdisr3;       /* Device disable control 3 */
  46         u32     devdisr4;       /* Device disable control 4 */
  47         u32     devdisr5;       /* Device disable control 5 */
  48         u32     devdisr6;       /* Device disable control 6 */
  49         u32     devdisr7;       /* Device disable control 7 */
  50         u8      res_08c[0x90-0x8c];
  51         u32     coredisru;      /* uppper portion for support of 64 cores */
  52         u32     coredisrl;      /* lower portion for support of 64 cores */
  53         u8      res_098[0xa0-0x98];
  54         u32     pvr;            /* Processor version */
  55         u32     svr;            /* System version */
  56         u32     mvr;            /* Manufacturing version */
  57         u8      res_0ac[0x100-0xac];
  58         u32     rcwsr[32];      /* Reset control word status */
  59
  60 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT   2
  61 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK    0x1f
  62 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT   10
  63 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK    0x3f
  64 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT  18
  65 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK   0x3f
  66 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x00FF0000
  67 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
  68 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0xFF000000
  69 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  24
  70
  71         u8      res_180[0x200-0x180];
  72         u32     scratchrw[32];  /* Scratch Read/Write */
  73         u8      res_280[0x300-0x280];
  74         u32     scratchw1r[4];  /* Scratch Read (Write once) */
  75         u8      res_310[0x400-0x310];
  76         u32     bootlocptrl;    /* Boot location pointer low-order addr */
  77         u32     bootlocptrh;    /* Boot location pointer high-order addr */
  78         u8      res_408[0x500-0x408];
  79         u8      res_500[0x740-0x500];   /* add more registers when needed */
  80         u32     tp_ityp[64];    /* Topology Initiator Type Register */
  81         struct {
  82                 u32     upper;
  83                 u32     lower;
  84         } tp_cluster[3];        /* Core Cluster n Topology Register */
  85         u8      res_858[0x1000-0x858];
  86 };
  87
  88 #define TP_ITYP_AV              0x00000001      /* Initiator available */
  89 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
  90 #define TP_ITYP_TYPE_ARM        0x0
  91 #define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
  92 #define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
  93 #define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
  94 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
  95 #define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
  96 #define TY_ITYP_VER_A7          0x1
  97 #define TY_ITYP_VER_A53         0x2
  98 #define TY_ITYP_VER_A57         0x3
  99
 100 #define TP_CLUSTER_EOC          0x80000000      /* end of clusters */
 101 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
 102 #define TP_INIT_PER_CLUSTER     4
 103
 104 struct ccsr_clk_cluster_group {
 105         struct {
 106                 u8      res_00[0x10];
 107                 u32     csr;
 108                 u8      res_14[0x20-0x14];
 109         } hwncsr[3];
 110         u8      res_60[0x80-0x60];
 111         struct {
 112                 u32     gsr;
 113                 u8      res_84[0xa0-0x84];
 114         } pllngsr[3];
 115         u8      res_e0[0x100-0xe0];
 116 };
 117
 118 struct ccsr_clk_ctrl {
 119         struct {
 120                 u32 csr;        /* core cluster n clock control status */
 121                 u8  res_04[0x20-0x04];
 122         } clkcncsr[8];
 123 };
 124
 125 struct ccsr_reset {
 126         u32 rstcr;                      /* 0x000 */
 127         u32 rstcrsp;                    /* 0x004 */
 128         u8 res_008[0x10-0x08];          /* 0x008 */
 129         u32 rstrqmr1;                   /* 0x010 */
 130         u32 rstrqmr2;                   /* 0x014 */
 131         u32 rstrqsr1;                   /* 0x018 */
 132         u32 rstrqsr2;                   /* 0x01c */
 133         u32 rstrqwdtmrl;                /* 0x020 */
 134         u32 rstrqwdtmru;                /* 0x024 */
 135         u8 res_028[0x30-0x28];          /* 0x028 */
 136         u32 rstrqwdtsrl;                /* 0x030 */
 137         u32 rstrqwdtsru;                /* 0x034 */
 138         u8 res_038[0x60-0x38];          /* 0x038 */
 139         u32 brrl;                       /* 0x060 */
 140         u32 brru;                       /* 0x064 */
 141         u8 res_068[0x80-0x68];          /* 0x068 */
 142         u32 pirset;                     /* 0x080 */
 143         u32 pirclr;                     /* 0x084 */
 144         u8 res_088[0x90-0x88];          /* 0x088 */
 145         u32 brcorenbr;                  /* 0x090 */
 146         u8 res_094[0x100-0x94];         /* 0x094 */
 147         u32 rcw_reqr;                   /* 0x100 */
 148         u32 rcw_completion;             /* 0x104 */
 149         u8 res_108[0x110-0x108];        /* 0x108 */
 150         u32 pbi_reqr;                   /* 0x110 */
 151         u32 pbi_completion;             /* 0x114 */
 152         u8 res_118[0xa00-0x118];        /* 0x118 */
 153         u32 qmbm_warmrst;               /* 0xa00 */
 154         u32 soc_warmrst;                /* 0xa04 */
 155         u8 res_a08[0xbf8-0xa08];        /* 0xa08 */
 156         u32 ip_rev1;                    /* 0xbf8 */
 157         u32 ip_rev2;                    /* 0xbfc */
 158 };
 159 #endif /* __ARCH_FSL_LSCH3_IMMAP_H */