3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef __ASM_ARCH_MX31_IMX_REGS_H
25 #define __ASM_ARCH_MX31_IMX_REGS_H
27 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
28 #include <asm/types.h>
30 /* Clock control module registers */
31 struct clock_control_regs {
71 /* Watchdog Timer (WDOG) registers */
72 #define WDOG_ENABLE (1 << 2)
73 #define WDOG_WT_SHIFT 8
74 #define WDOG_WDZST (1 << 0)
77 u16 wcr; /* Control */
78 u16 wsr; /* Service */
79 u16 wrsr; /* Reset Status */
82 /* IIM Control Registers */
101 struct mx3_cpu_type {
106 #define IOMUX_PADNUM_MASK 0x1ff
107 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
110 * various IOMUX pad functions
112 enum iomux_pad_config {
113 PAD_CTL_NOLOOPBACK = 0x0 << 9,
114 PAD_CTL_LOOPBACK = 0x1 << 9,
115 PAD_CTL_PKE_NONE = 0x0 << 8,
116 PAD_CTL_PKE_ENABLE = 0x1 << 8,
117 PAD_CTL_PUE_KEEPER = 0x0 << 7,
118 PAD_CTL_PUE_PUD = 0x1 << 7,
119 PAD_CTL_100K_PD = 0x0 << 5,
120 PAD_CTL_100K_PU = 0x1 << 5,
121 PAD_CTL_47K_PU = 0x2 << 5,
122 PAD_CTL_22K_PU = 0x3 << 5,
123 PAD_CTL_HYS_CMOS = 0x0 << 4,
124 PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
125 PAD_CTL_ODE_CMOS = 0x0 << 3,
126 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
127 PAD_CTL_DRV_NORMAL = 0x0 << 1,
128 PAD_CTL_DRV_HIGH = 0x1 << 1,
129 PAD_CTL_DRV_MAX = 0x2 << 1,
130 PAD_CTL_SRE_SLOW = 0x0 << 0,
131 PAD_CTL_SRE_FAST = 0x1 << 0
135 * This enumeration is constructed based on the Section
136 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
137 * value is constructed based on the rules described above.
141 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
142 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
143 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
144 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
145 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
146 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
147 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
148 MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
149 MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
150 MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
151 MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
152 MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
153 MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
154 MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
155 MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
156 MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
157 MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
158 MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
159 MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
160 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
161 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
162 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
163 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
164 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
165 MX31_PIN_READ = IOMUX_PIN(0xff, 24),
166 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
167 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
168 MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
169 MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
170 MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
171 MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
172 MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
173 MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
174 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
175 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
176 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
177 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
178 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
179 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
180 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
181 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
182 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
183 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
184 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
185 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
186 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
187 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
188 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
189 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
190 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
191 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
192 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
193 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
194 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
195 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
196 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
197 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
198 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
199 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
200 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
201 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
202 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
203 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
204 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
205 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
206 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
207 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
208 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
209 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
210 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
211 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
212 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
213 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
214 MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
215 MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
216 MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
217 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
218 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
219 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
220 MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
221 MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
222 MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
223 MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
224 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
225 MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
226 MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
227 MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
228 MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
229 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
230 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
231 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
232 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
233 MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
234 MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
235 MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
236 MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
237 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
238 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
239 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
240 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
241 MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
242 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
243 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
244 MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
245 MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
246 MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
247 MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
248 MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
249 MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
250 MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
251 MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
252 MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
253 MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
254 MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
255 MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
256 MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
257 MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
258 MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
259 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
260 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
261 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
262 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
263 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
264 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
265 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
266 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
267 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
268 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
269 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
270 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
271 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
272 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
273 MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
274 MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
275 MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
276 MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
277 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
278 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
279 MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
280 MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
281 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
282 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
283 MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
284 MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
285 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
286 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
287 MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
288 MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
289 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
290 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
291 MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
292 MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
293 MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
294 MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
295 MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
296 MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
297 MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
298 MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
299 MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
300 MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
301 MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
302 MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
303 MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
304 MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
305 MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
306 MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
307 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
308 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
309 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
310 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
311 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
312 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
313 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
314 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
315 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
316 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
317 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
318 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
319 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
320 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
321 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
322 MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
323 MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
324 MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
325 MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
326 MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
327 MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
328 MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
329 MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
330 MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
331 MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
332 MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
333 MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
334 MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
335 MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
336 MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
337 MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
338 MX31_PIN_NFRB = IOMUX_PIN(16, 197),
339 MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
340 MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
341 MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
342 MX31_PIN_NFALE = IOMUX_PIN(12, 201),
343 MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
344 MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
345 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
346 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
347 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
348 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
349 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
350 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
351 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
352 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
353 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
354 MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
355 MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
356 MX31_PIN_RW = IOMUX_PIN(0xff, 215),
357 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
358 MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
359 MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
360 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
361 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
362 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
363 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
364 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
365 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
366 MX31_PIN_OE = IOMUX_PIN(0xff, 225),
367 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
368 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
369 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
370 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
371 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
372 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
373 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
374 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
375 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
376 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
377 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
378 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
379 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
380 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
381 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
382 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
383 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
384 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
385 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
386 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
387 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
388 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
389 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
390 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
391 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
392 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
393 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
394 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
395 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
396 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
397 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
398 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
399 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
400 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
401 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
402 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
403 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
404 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
405 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
406 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
407 MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
408 MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
409 MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
410 MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
411 MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
412 MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
413 MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
414 MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
415 MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
416 MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
417 MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
418 MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
419 MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
420 MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
421 MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
422 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
423 MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
424 MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
425 MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
426 MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
427 MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
428 MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
429 MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
430 MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
431 MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
432 MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
433 MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
434 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
435 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
436 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
437 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
438 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
439 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
440 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
441 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
442 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
443 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
444 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
445 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
446 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
447 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
448 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
449 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
450 MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
451 MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
452 MX31_PIN_STX0 = IOMUX_PIN(33, 311),
453 MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
454 MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
455 MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
456 MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
457 MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
458 MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317),
459 MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318),
460 MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319),
461 MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320),
462 MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321),
463 MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322),
464 MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323),
465 MX31_PIN_PWMO = IOMUX_PIN(9, 324),
466 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
467 MX31_PIN_COMPARE = IOMUX_PIN(8, 326),
468 MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
472 * various IOMUX general purpose functions
475 MUX_PGP_FIRI = 1 << 0,
476 MUX_DDR_MODE = 1 << 1,
477 MUX_PGP_CSPI_BB = 1 << 2,
478 MUX_PGP_ATA_1 = 1 << 3,
479 MUX_PGP_ATA_2 = 1 << 4,
480 MUX_PGP_ATA_3 = 1 << 5,
481 MUX_PGP_ATA_4 = 1 << 6,
482 MUX_PGP_ATA_5 = 1 << 7,
483 MUX_PGP_ATA_6 = 1 << 8,
484 MUX_PGP_ATA_7 = 1 << 9,
485 MUX_PGP_ATA_8 = 1 << 10,
486 MUX_PGP_UH2 = 1 << 11,
487 MUX_SDCTL_CSD0_SEL = 1 << 12,
488 MUX_SDCTL_CSD1_SEL = 1 << 13,
489 MUX_CSPI1_UART3 = 1 << 14,
490 MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
491 MUX_TAMPER_DETECT_EN = 1 << 16,
492 MUX_PGP_USB_4WIRE = 1 << 17,
493 MUX_PGP_USB_COMMON = 1 << 18,
494 MUX_SDHC_MEMSTICK1 = 1 << 19,
495 MUX_SDHC_MEMSTICK2 = 1 << 20,
496 MUX_PGP_SPLL_BYP = 1 << 21,
497 MUX_PGP_UPLL_BYP = 1 << 22,
498 MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
499 MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
500 MUX_CSPI3_UART5_SEL = 1 << 25,
501 MUX_PGP_ATA_9 = 1 << 26,
502 MUX_PGP_USB_SUSPEND = 1 << 27,
503 MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
504 MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
505 MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
506 MUX_CLKO_DDR_MODE = 1 << 31,
509 /* Bit definitions for RCSR register in CCM */
510 #define CCM_RCSR_NF16B (1 << 31)
511 #define CCM_RCSR_NFMS (1 << 30)
513 /* WEIM CS control registers */
514 struct mx31_weim_cscr {
522 struct mx31_weim_cscr cscr[6];
525 /* ESD control registers */
538 #define __REG(x) (*((volatile u32 *)(x)))
539 #define __REG16(x) (*((volatile u16 *)(x)))
540 #define __REG8(x) (*((volatile u8 *)(x)))
542 #define CCM_BASE 0x53f80000
543 #define CCM_CCMR (CCM_BASE + 0x00)
544 #define CCM_PDR0 (CCM_BASE + 0x04)
545 #define CCM_PDR1 (CCM_BASE + 0x08)
546 #define CCM_RCSR (CCM_BASE + 0x0c)
547 #define CCM_MPCTL (CCM_BASE + 0x10)
548 #define CCM_UPCTL (CCM_BASE + 0x14)
549 #define CCM_SPCTL (CCM_BASE + 0x18)
550 #define CCM_COSR (CCM_BASE + 0x1C)
551 #define CCM_CGR0 (CCM_BASE + 0x20)
552 #define CCM_CGR1 (CCM_BASE + 0x24)
553 #define CCM_CGR2 (CCM_BASE + 0x28)
555 #define CCMR_MDS (1 << 7)
556 #define CCMR_SBYCS (1 << 4)
557 #define CCMR_MPE (1 << 3)
558 #define CCMR_PRCS_MASK (3 << 1)
559 #define CCMR_FPM (1 << 1)
560 #define CCMR_CKIH (2 << 1)
562 #define MX31_IIM_BASE_ADDR 0x5001C000
564 #define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
565 #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
566 #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
567 #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
568 #define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
569 #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
570 #define PDR0_MCU_PODF(x) ((x) & 0x7)
572 #define PLL_PD(x) (((x) & 0xf) << 26)
573 #define PLL_MFD(x) (((x) & 0x3ff) << 16)
574 #define PLL_MFI(x) (((x) & 0xf) << 10)
575 #define PLL_MFN(x) (((x) & 0x3ff) << 0)
577 #define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff)
578 #define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f)
579 #define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7)
580 #define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7)
581 #define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3)
582 #define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7)
583 #define GET_PDR0_MCU_PODF(x) ((x) & 0x7)
585 #define GET_PLL_PD(x) (((x) >> 26) & 0xf)
586 #define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff)
587 #define GET_PLL_MFI(x) (((x) >> 10) & 0xf)
588 #define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff)
591 #define WEIM_ESDCTL0 0xB8001000
592 #define WEIM_ESDCFG0 0xB8001004
593 #define WEIM_ESDCTL1 0xB8001008
594 #define WEIM_ESDCFG1 0xB800100C
595 #define WEIM_ESDMISC 0xB8001010
597 #define ESDCTL_SDE (1 << 31)
598 #define ESDCTL_CMD_RW (0 << 28)
599 #define ESDCTL_CMD_PRECHARGE (1 << 28)
600 #define ESDCTL_CMD_AUTOREFRESH (2 << 28)
601 #define ESDCTL_CMD_LOADMODEREG (3 << 28)
602 #define ESDCTL_CMD_MANUALREFRESH (4 << 28)
603 #define ESDCTL_ROW_13 (2 << 24)
604 #define ESDCTL_ROW(x) ((x) << 24)
605 #define ESDCTL_COL_9 (1 << 20)
606 #define ESDCTL_COL(x) ((x) << 20)
607 #define ESDCTL_DSIZ(x) ((x) << 16)
608 #define ESDCTL_SREFR(x) ((x) << 13)
609 #define ESDCTL_PWDT(x) ((x) << 10)
610 #define ESDCTL_FP(x) ((x) << 8)
611 #define ESDCTL_BL(x) ((x) << 7)
612 #define ESDCTL_PRCT(x) ((x) << 0)
614 #define ESDCTL_BASE_ADDR 0xB8001000
616 /* 13 fields of the upper CS control register */
617 #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
618 cnc, wsc, ew, wws, edc) \
619 ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
620 (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
621 (wws) << 4 | (edc) << 0)
622 /* 12 fields of the lower CS control register */
623 #define CSCR_L(oea, oen, ebwa, ebwn, \
624 csa, ebc, dsz, csn, psr, cre, wrap, csen) \
625 ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
626 (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
627 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
628 /* 14 fields of the additional CS control register */
629 #define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
630 wwu, age, cnc2, fce) \
631 ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
632 (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
633 (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
634 (age) << 2 | (cnc2) << 1 | (fce) << 0)
636 #define WEIM_BASE 0xb8002000
638 #define IOMUXC_BASE 0x43FAC000
639 #define IOMUXC_GPR (IOMUXC_BASE + 0x8)
640 #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
641 #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
643 #define IPU_BASE 0x53fc0000
644 #define IPU_CONF IPU_BASE
646 #define IPU_CONF_PXL_ENDIAN (1<<8)
647 #define IPU_CONF_DU_EN (1<<7)
648 #define IPU_CONF_DI_EN (1<<6)
649 #define IPU_CONF_ADC_EN (1<<5)
650 #define IPU_CONF_SDC_EN (1<<4)
651 #define IPU_CONF_PF_EN (1<<3)
652 #define IPU_CONF_ROT_EN (1<<2)
653 #define IPU_CONF_IC_EN (1<<1)
654 #define IPU_CONF_SCI_EN (1<<0)
656 #define ARM_PPMRR 0x40000015
658 #define WDOG_BASE 0x53FDC000
663 #define GPIO1_BASE_ADDR 0x53FCC000
664 #define GPIO2_BASE_ADDR 0x53FD0000
665 #define GPIO3_BASE_ADDR 0x53FA4000
666 #define GPIO_DR 0x00000000 /* data register */
667 #define GPIO_GDIR 0x00000004 /* direction register */
668 #define GPIO_PSR 0x00000008 /* pad status register */
671 * Signal Multiplexing (IOMUX)
674 /* bits in the SW_MUX_CTL registers */
675 #define MUX_CTL_OUT_GPIO_DR (0 << 4)
676 #define MUX_CTL_OUT_FUNC (1 << 4)
677 #define MUX_CTL_OUT_ALT1 (2 << 4)
678 #define MUX_CTL_OUT_ALT2 (3 << 4)
679 #define MUX_CTL_OUT_ALT3 (4 << 4)
680 #define MUX_CTL_OUT_ALT4 (5 << 4)
681 #define MUX_CTL_OUT_ALT5 (6 << 4)
682 #define MUX_CTL_OUT_ALT6 (7 << 4)
683 #define MUX_CTL_IN_NONE (0 << 0)
684 #define MUX_CTL_IN_GPIO (1 << 0)
685 #define MUX_CTL_IN_FUNC (2 << 0)
686 #define MUX_CTL_IN_ALT1 (4 << 0)
687 #define MUX_CTL_IN_ALT2 (8 << 0)
689 #define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
690 #define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
691 #define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
692 #define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
694 /* Register offsets based on IOMUXC_BASE */
696 #define MUX_CTL_CSPI3_MISO 0x0c
697 #define MUX_CTL_CSPI3_SCLK 0x0d
698 #define MUX_CTL_CSPI3_SPI_RDY 0x0e
699 #define MUX_CTL_CSPI3_MOSI 0x13
701 #define MUX_CTL_USBH2_DATA1 0x40
702 #define MUX_CTL_USBH2_DIR 0x44
703 #define MUX_CTL_USBH2_STP 0x45
704 #define MUX_CTL_USBH2_NXT 0x46
705 #define MUX_CTL_USBH2_DATA0 0x47
706 #define MUX_CTL_USBH2_CLK 0x4B
708 #define MUX_CTL_TXD2 0x70
709 #define MUX_CTL_RTS2 0x71
710 #define MUX_CTL_CTS2 0x72
711 #define MUX_CTL_RXD2 0x77
713 #define MUX_CTL_RTS1 0x7c
714 #define MUX_CTL_CTS1 0x7d
715 #define MUX_CTL_DTR_DCE1 0x7e
716 #define MUX_CTL_DSR_DCE1 0x7f
717 #define MUX_CTL_CSPI2_SCLK 0x80
718 #define MUX_CTL_CSPI2_SPI_RDY 0x81
719 #define MUX_CTL_RXD1 0x82
720 #define MUX_CTL_TXD1 0x83
721 #define MUX_CTL_CSPI2_MISO 0x84
722 #define MUX_CTL_CSPI2_SS0 0x85
723 #define MUX_CTL_CSPI2_SS1 0x86
724 #define MUX_CTL_CSPI2_SS2 0x87
725 #define MUX_CTL_CSPI1_SS2 0x88
726 #define MUX_CTL_CSPI1_SCLK 0x89
727 #define MUX_CTL_CSPI1_SPI_RDY 0x8a
728 #define MUX_CTL_CSPI2_MOSI 0x8b
729 #define MUX_CTL_CSPI1_MOSI 0x8c
730 #define MUX_CTL_CSPI1_MISO 0x8d
731 #define MUX_CTL_CSPI1_SS0 0x8e
732 #define MUX_CTL_CSPI1_SS1 0x8f
733 #define MUX_CTL_STXD6 0x90
734 #define MUX_CTL_SRXD6 0x91
735 #define MUX_CTL_SCK6 0x92
736 #define MUX_CTL_SFS6 0x93
738 #define MUX_CTL_STXD3 0x9C
739 #define MUX_CTL_SRXD3 0x9D
740 #define MUX_CTL_SCK3 0x9E
741 #define MUX_CTL_SFS3 0x9F
743 #define MUX_CTL_NFC_WP 0xD0
744 #define MUX_CTL_NFC_CE 0xD1
745 #define MUX_CTL_NFC_RB 0xD2
746 #define MUX_CTL_NFC_WE 0xD4
747 #define MUX_CTL_NFC_RE 0xD5
748 #define MUX_CTL_NFC_ALE 0xD6
749 #define MUX_CTL_NFC_CLE 0xD7
752 #define MUX_CTL_CAPTURE 0x150
753 #define MUX_CTL_COMPARE 0x151
756 * Helper macros for the MUX_[contact name]__[pin function] macros
758 #define IOMUX_MODE_POS 9
759 #define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
762 * These macros can be used in mx31_gpio_mux() and have the form
763 * MUX_[contact name]__[pin function]
765 #define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
766 #define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
767 #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
768 #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
770 #define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
771 #define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
772 #define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
773 #define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
775 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
776 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
777 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
778 #define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
779 #define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
780 #define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
781 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
782 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
784 #define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
785 #define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
786 #define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
787 #define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
788 #define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
789 #define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
790 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
791 #define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
793 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
794 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
796 /* PAD control registers for SDR/DDR */
797 #define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
798 #define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
799 #define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
800 #define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
801 #define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
802 #define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
803 #define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
804 #define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
805 #define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
806 #define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
807 #define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
808 #define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
809 #define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
810 #define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
811 #define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
812 #define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
813 #define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
814 #define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
815 #define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
816 #define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
817 #define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
818 #define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
819 #define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
820 #define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
821 #define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
822 #define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
823 #define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
824 #define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
825 #define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
828 * Memory regions and CS
830 #define IPU_MEM_BASE 0x70000000
831 #define CSD0_BASE 0x80000000
832 #define CSD1_BASE 0x90000000
833 #define CS0_BASE 0xA0000000
834 #define CS1_BASE 0xA8000000
835 #define CS2_BASE 0xB0000000
836 #define CS3_BASE 0xB2000000
837 #define CS4_BASE 0xB4000000
838 #define CS4_PSRAM_BASE 0xB5000000
839 #define CS5_BASE 0xB6000000
840 #define PCMCIA_MEM_BASE 0xC0000000
845 #define NFC_BASE_ADDR 0xB8000000
848 * Internal RAM (16KB)
850 #define IRAM_BASE_ADDR 0x1FFFC000
851 #define IRAM_SIZE (16 * 1024)
853 #define MX31_AIPS1_BASE_ADDR 0x43f00000
854 #define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
857 /* values for portsc field */
858 #define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
859 #define MXC_EHCI_FORCE_FS (1 << 24)
860 #define MXC_EHCI_UTMI_8BIT (0 << 28)
861 #define MXC_EHCI_UTMI_16BIT (1 << 28)
862 #define MXC_EHCI_SERIAL (1 << 29)
863 #define MXC_EHCI_MODE_UTMI (0 << 30)
864 #define MXC_EHCI_MODE_PHILIPS (1 << 30)
865 #define MXC_EHCI_MODE_ULPI (2 << 30)
866 #define MXC_EHCI_MODE_SERIAL (3 << 30)
868 /* values for flags field */
869 #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
870 #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
871 #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
872 #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
873 #define MXC_EHCI_INTERFACE_MASK (0xf)
875 #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
876 #define MXC_EHCI_TTL_ENABLED (1 << 6)
878 #define MXC_EHCI_INTERNAL_PHY (1 << 7)
879 #define MXC_EHCI_IPPUE_DOWN (1 << 8)
880 #define MXC_EHCI_IPPUE_UP (1 << 9)
882 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */