arch/arm/include/asm/arch-mx6/imx-regs.h

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
  20 #define __ASM_ARCH_MX6_IMX_REGS_H__
  21
  22 #define ARCH_MXC
  23
  24 #define CONFIG_SYS_CACHELINE_SIZE       32
  25
  26 #define ROMCP_ARB_BASE_ADDR             0x00000000
  27 #define ROMCP_ARB_END_ADDR              0x000FFFFF
  28
  29 #ifdef CONFIG_MX6SL
  30 #define GPU_2D_ARB_BASE_ADDR            0x02200000
  31 #define GPU_2D_ARB_END_ADDR             0x02203FFF
  32 #define OPENVG_ARB_BASE_ADDR            0x02204000
  33 #define OPENVG_ARB_END_ADDR             0x02207FFF
  34 #else
  35 #define CAAM_ARB_BASE_ADDR              0x00100000
  36 #define CAAM_ARB_END_ADDR               0x00103FFF
  37 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
  38 #define APBH_DMA_ARB_END_ADDR           0x00117FFF
  39 #define HDMI_ARB_BASE_ADDR              0x00120000
  40 #define HDMI_ARB_END_ADDR               0x00128FFF
  41 #define GPU_3D_ARB_BASE_ADDR            0x00130000
  42 #define GPU_3D_ARB_END_ADDR             0x00133FFF
  43 #define GPU_2D_ARB_BASE_ADDR            0x00134000
  44 #define GPU_2D_ARB_END_ADDR             0x00137FFF
  45 #define DTCP_ARB_BASE_ADDR              0x00138000
  46 #define DTCP_ARB_END_ADDR               0x0013BFFF
  47 #endif  /* CONFIG_MX6SL */
  48 /* GPV - PL301 configuration ports */
  49 #ifdef CONFIG_MX6SL
  50 #define GPV2_BASE_ADDR                  0x00D00000
  51 #else
  52 #define GPV2_BASE_ADDR                  0x00200000
  53 #endif
  54
  55 #define GPV3_BASE_ADDR                  0x00300000
  56 #define GPV4_BASE_ADDR                  0x00800000
  57 #define IRAM_BASE_ADDR                  0x00900000
  58 #define SCU_BASE_ADDR                   0x00A00000
  59 #define IC_INTERFACES_BASE_ADDR         0x00A00100
  60 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
  61 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
  62 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
  63 #define GPV0_BASE_ADDR                  0x00B00000
  64 #define GPV1_BASE_ADDR                  0x00C00000
  65 #define PCIE_ARB_BASE_ADDR              0x01000000
  66 #define PCIE_ARB_END_ADDR               0x01FFFFFF
  67
  68 #define AIPS1_ARB_BASE_ADDR             0x02000000
  69 #define AIPS1_ARB_END_ADDR              0x020FFFFF
  70 #define AIPS2_ARB_BASE_ADDR             0x02100000
  71 #define AIPS2_ARB_END_ADDR              0x021FFFFF
  72 #define SATA_ARB_BASE_ADDR              0x02200000
  73 #define SATA_ARB_END_ADDR               0x02203FFF
  74 #define OPENVG_ARB_BASE_ADDR            0x02204000
  75 #define OPENVG_ARB_END_ADDR             0x02207FFF
  76 #define HSI_ARB_BASE_ADDR               0x02208000
  77 #define HSI_ARB_END_ADDR                0x0220BFFF
  78 #define IPU1_ARB_BASE_ADDR              0x02400000
  79 #define IPU1_ARB_END_ADDR               0x027FFFFF
  80 #define IPU2_ARB_BASE_ADDR              0x02800000
  81 #define IPU2_ARB_END_ADDR               0x02BFFFFF
  82 #define WEIM_ARB_BASE_ADDR              0x08000000
  83 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
  84
  85 #ifdef CONFIG_MX6SL
  86 #define MMDC0_ARB_BASE_ADDR             0x80000000
  87 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
  88 #define MMDC1_ARB_BASE_ADDR             0xC0000000
  89 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
  90 #else
  91 #define MMDC0_ARB_BASE_ADDR             0x10000000
  92 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
  93 #define MMDC1_ARB_BASE_ADDR             0x80000000
  94 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
  95 #endif
  96
  97 #define IPU_SOC_BASE_ADDR               IPU1_ARB_BASE_ADDR
  98 #define IPU_SOC_OFFSET                  0x00200000
  99
 100 /* Defines for Blocks connected via AIPS (SkyBlue) */
 101 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
 102 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
 103 #define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
 104 #define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
 105
 106 #define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
 107 #define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
 108 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
 109 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
 110 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
 111 #ifdef CONFIG_MX6SL
 112 #define UART5_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x18000)
 113 #define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
 114 #define UART2_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x24000)
 115 #define SSI1_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x28000)
 116 #define SSI2_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x2C000)
 117 #define SSI3_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x30000)
 118 #define UART3_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x34000)
 119 #define UART4_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x38000)
 120 #else
 121 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
 122 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
 123 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
 124 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
 125 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
 126 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
 127 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
 128 #endif
 129
 130 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
 131 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
 132 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
 133
 134 #define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
 135 #define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
 136 #define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
 137 #define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
 138 #define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
 139 #define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
 140 #define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
 141 #define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
 142 #define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
 143 #define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
 144 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
 145 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
 146 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
 147 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
 148 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
 149 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
 150 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
 151 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
 152 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
 153 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
 154 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
 155 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
 156 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
 157 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
 158 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
 159 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
 160 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
 161 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
 162 #ifdef CONFIG_MX6SL
 163 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
 164 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 165 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
 166 #else
 167 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
 168 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 169 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
 170 #endif
 171
 172 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
 173 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 174 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 175 #define ARM_BASE_ADDR               (ATZ2_BASE_ADDR + 0x40000)
 176 #ifdef CONFIG_MX6SL
 177 #define USBO2H_PL301_IPS_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x0000)
 178 #define USBO2H_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
 179 #else
 180 #define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
 181 #define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
 182 #endif
 183
 184 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
 185 #ifdef CONFIG_MX6SL
 186 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
 187 #else
 188 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
 189 #endif
 190
 191 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
 192 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
 193 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
 194 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
 195 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
 196 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
 197 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
 198 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
 199 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
 200 #ifdef CONFIG_MX6SL
 201 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
 202 #else
 203 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
 204 #endif
 205
 206 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
 207 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
 208 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
 209 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 210 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
 211 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 212 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
 213 #define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
 214 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
 215 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
 216 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
 217 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
 218 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
 219 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 220 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 221 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
 222 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 223 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 224
 225 #define CHIP_REV_1_0                 0x10
 226 #define IRAM_SIZE                    0x00040000
 227 #define IMX_IIM_BASE                 OCOTP_BASE_ADDR
 228 #define FEC_QUIRK_ENET_MAC
 229
 230 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 231 #include <asm/types.h>
 232
 233 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 234
 235 /* System Reset Controller (SRC) */
 236 struct src {
 237         u32     scr;
 238         u32     sbmr1;
 239         u32     srsr;
 240         u32     reserved1[2];
 241         u32     sisr;
 242         u32     simr;
 243         u32     sbmr2;
 244         u32     gpr1;
 245         u32     gpr2;
 246         u32     gpr3;
 247         u32     gpr4;
 248         u32     gpr5;
 249         u32     gpr6;
 250         u32     gpr7;
 251         u32     gpr8;
 252         u32     gpr9;
 253         u32     gpr10;
 254 };
 255
 256 /* OCOTP Registers */
 257 struct ocotp_regs {
 258         u32     reserved[0x198];
 259         u32     gp1;    /* 0x660 */
 260 };
 261
 262 /* GPR3 bitfields */
 263 #define IOMUXC_GPR3_GPU_DBG_OFFSET              29
 264 #define IOMUXC_GPR3_GPU_DBG_MASK                (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
 265 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET     28
 266 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK       (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
 267 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET     27
 268 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK       (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
 269 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET  26
 270 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK    (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
 271 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET  25
 272 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK    (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
 273 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET            21
 274 #define IOMUXC_GPR3_OCRAM_CTL_MASK              (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
 275 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET         17
 276 #define IOMUXC_GPR3_OCRAM_STATUS_MASK           (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
 277 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET     16
 278 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
 279 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET     15
 280 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
 281 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET     14
 282 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
 283 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET     13
 284 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
 285 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET     12
 286 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK       (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
 287 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET     11
 288 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK       (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
 289 #define IOMUXC_GPR3_IPU_DIAG_OFFSET             10
 290 #define IOMUXC_GPR3_IPU_DIAG_MASK               (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
 291
 292 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0    0
 293 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1    1
 294 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0    2
 295 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1    3
 296
 297 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET        8
 298 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK          (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
 299
 300 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET        6
 301 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK          (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
 302
 303 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET         4
 304 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK           (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
 305
 306 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET         2
 307 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK           (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
 308
 309
 310 struct iomuxc {
 311         u32 gpr[14];
 312         u32 omux[5];
 313         /* mux and pad registers */
 314 };
 315
 316 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET            20
 317 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK              (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 318 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET               16
 319 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK                 (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
 320
 321 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET                 15
 322 #define IOMUXC_GPR2_BGREF_RRMODE_MASK                   (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 323 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES           (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 324 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES           (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 325 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH   0
 326 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW    1
 327
 328 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET              10
 329 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK                (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 330 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH         (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 331 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW          (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 332
 333 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET              9
 334 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK                (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 335 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH         (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 336 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW          (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 337
 338 #define IOMUXC_GPR2_BITMAP_SPWG 0
 339 #define IOMUXC_GPR2_BITMAP_JEIDA        1
 340
 341 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET              8
 342 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK                (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 343 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA               (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 344 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG                (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 345
 346 #define IOMUXC_GPR2_DATA_WIDTH_18       0
 347 #define IOMUXC_GPR2_DATA_WIDTH_24       1
 348
 349 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET               7
 350 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK                 (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 351 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT                (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 352 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT                (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 353
 354 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET              6
 355 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK                (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 356 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA               (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 357 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG                (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 358
 359 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET               5
 360 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK                 (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 361 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT                (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 362 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT                (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 363
 364 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET                4
 365 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK                  (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
 366
 367 #define IOMUXC_GPR2_MODE_DISABLED       0
 368 #define IOMUXC_GPR2_MODE_ENABLED_DI0    1
 369 #define IOMUXC_GPR2_MODE_ENABLED_DI1    2
 370
 371 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET                2
 372 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK                  (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 373 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED              (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 374 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0           (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 375 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1           (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 376
 377 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET                0
 378 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK                  (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 379 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED              (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 380 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0           (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 381 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1           (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 382
 383 /* ECSPI registers */
 384 struct cspi_regs {
 385         u32 rxdata;
 386         u32 txdata;
 387         u32 ctrl;
 388         u32 cfg;
 389         u32 intr;
 390         u32 dma;
 391         u32 stat;
 392         u32 period;
 393 };
 394
 395 /*
 396  * CSPI register definitions
 397  */
 398 #define MXC_ECSPI
 399 #define MXC_CSPICTRL_EN         (1 << 0)
 400 #define MXC_CSPICTRL_MODE       (1 << 1)
 401 #define MXC_CSPICTRL_XCH        (1 << 2)
 402 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
 403 #define MXC_CSPICTRL_CHIPSELECT(x)      (((x) & 0x3) << 12)
 404 #define MXC_CSPICTRL_BITCOUNT(x)        (((x) & 0xfff) << 20)
 405 #define MXC_CSPICTRL_PREDIV(x)  (((x) & 0xF) << 12)
 406 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
 407 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
 408 #define MXC_CSPICTRL_MAXBITS    0xfff
 409 #define MXC_CSPICTRL_TC         (1 << 7)
 410 #define MXC_CSPICTRL_RXOVF      (1 << 6)
 411 #define MXC_CSPIPERIOD_32KHZ    (1 << 15)
 412 #define MAX_SPI_BYTES   32
 413
 414 /* Bit position inside CTRL register to be associated with SS */
 415 #define MXC_CSPICTRL_CHAN       18
 416
 417 /* Bit position inside CON register to be associated with SS */
 418 #define MXC_CSPICON_POL         4
 419 #define MXC_CSPICON_PHA         0
 420 #define MXC_CSPICON_SSPOL       12
 421 #ifdef CONFIG_MX6SL
 422 #define MXC_SPI_BASE_ADDRESSES \
 423         ECSPI1_BASE_ADDR, \
 424         ECSPI2_BASE_ADDR, \
 425         ECSPI3_BASE_ADDR, \
 426         ECSPI4_BASE_ADDR
 427 #else
 428 #define MXC_SPI_BASE_ADDRESSES \
 429         ECSPI1_BASE_ADDR, \
 430         ECSPI2_BASE_ADDR, \
 431         ECSPI3_BASE_ADDR, \
 432         ECSPI4_BASE_ADDR, \
 433         ECSPI5_BASE_ADDR
 434 #endif
 435
 436 struct iim_regs {
 437         u32     ctrl;
 438         u32     ctrl_set;
 439         u32     ctrl_clr;
 440         u32     ctrl_tog;
 441         u32     timing;
 442         u32     rsvd0[3];
 443         u32     data;
 444         u32     rsvd1[3];
 445         u32     read_ctrl;
 446         u32     rsvd2[3];
 447         u32     fuse_data;
 448         u32     rsvd3[3];
 449         u32     sticky;
 450         u32     rsvd4[3];
 451         u32     scs;
 452         u32     scs_set;
 453         u32     scs_clr;
 454         u32     scs_tog;
 455         u32     crc_addr;
 456         u32     rsvd5[3];
 457         u32     crc_value;
 458         u32     rsvd6[3];
 459         u32     version;
 460         u32     rsvd7[0xdb];
 461
 462         struct fuse_bank {
 463                 u32     fuse_regs[0x20];
 464         } bank[15];
 465 };
 466
 467 struct fuse_bank4_regs {
 468         u32     sjc_resp_low;
 469         u32     rsvd0[3];
 470         u32     sjc_resp_high;
 471         u32     rsvd1[3];
 472         u32     mac_addr_low;
 473         u32     rsvd2[3];
 474         u32     mac_addr_high;
 475         u32     rsvd3[0x13];
 476 };
 477
 478 struct aipstz_regs {
 479         u32     mprot0;
 480         u32     mprot1;
 481         u32     rsvd[0xe];
 482         u32     opacr0;
 483         u32     opacr1;
 484         u32     opacr2;
 485         u32     opacr3;
 486         u32     opacr4;
 487 };
 488
 489 struct anatop_regs {
 490         u32     pll_sys;                /* 0x000 */
 491         u32     pll_sys_set;            /* 0x004 */
 492         u32     pll_sys_clr;            /* 0x008 */
 493         u32     pll_sys_tog;            /* 0x00c */
 494         u32     usb1_pll_480_ctrl;      /* 0x010 */
 495         u32     usb1_pll_480_ctrl_set;  /* 0x014 */
 496         u32     usb1_pll_480_ctrl_clr;  /* 0x018 */
 497         u32     usb1_pll_480_ctrl_tog;  /* 0x01c */
 498         u32     usb2_pll_480_ctrl;      /* 0x020 */
 499         u32     usb2_pll_480_ctrl_set;  /* 0x024 */
 500         u32     usb2_pll_480_ctrl_clr;  /* 0x028 */
 501         u32     usb2_pll_480_ctrl_tog;  /* 0x02c */
 502         u32     pll_528;                /* 0x030 */
 503         u32     pll_528_set;            /* 0x034 */
 504         u32     pll_528_clr;            /* 0x038 */
 505         u32     pll_528_tog;            /* 0x03c */
 506         u32     pll_528_ss;             /* 0x040 */
 507         u32     rsvd0[3];
 508         u32     pll_528_num;            /* 0x050 */
 509         u32     rsvd1[3];
 510         u32     pll_528_denom;          /* 0x060 */
 511         u32     rsvd2[3];
 512         u32     pll_audio;              /* 0x070 */
 513         u32     pll_audio_set;          /* 0x074 */
 514         u32     pll_audio_clr;          /* 0x078 */
 515         u32     pll_audio_tog;          /* 0x07c */
 516         u32     pll_audio_num;          /* 0x080 */
 517         u32     rsvd3[3];
 518         u32     pll_audio_denom;        /* 0x090 */
 519         u32     rsvd4[3];
 520         u32     pll_video;              /* 0x0a0 */
 521         u32     pll_video_set;          /* 0x0a4 */
 522         u32     pll_video_clr;          /* 0x0a8 */
 523         u32     pll_video_tog;          /* 0x0ac */
 524         u32     pll_video_num;          /* 0x0b0 */
 525         u32     rsvd5[3];
 526         u32     pll_video_denom;        /* 0x0c0 */
 527         u32     rsvd6[3];
 528         u32     pll_mlb;                /* 0x0d0 */
 529         u32     pll_mlb_set;            /* 0x0d4 */
 530         u32     pll_mlb_clr;            /* 0x0d8 */
 531         u32     pll_mlb_tog;            /* 0x0dc */
 532         u32     pll_enet;               /* 0x0e0 */
 533         u32     pll_enet_set;           /* 0x0e4 */
 534         u32     pll_enet_clr;           /* 0x0e8 */
 535         u32     pll_enet_tog;           /* 0x0ec */
 536         u32     pfd_480;                /* 0x0f0 */
 537         u32     pfd_480_set;            /* 0x0f4 */
 538         u32     pfd_480_clr;            /* 0x0f8 */
 539         u32     pfd_480_tog;            /* 0x0fc */
 540         u32     pfd_528;                /* 0x100 */
 541         u32     pfd_528_set;            /* 0x104 */
 542         u32     pfd_528_clr;            /* 0x108 */
 543         u32     pfd_528_tog;            /* 0x10c */
 544         u32     reg_1p1;                /* 0x110 */
 545         u32     reg_1p1_set;            /* 0x114 */
 546         u32     reg_1p1_clr;            /* 0x118 */
 547         u32     reg_1p1_tog;            /* 0x11c */
 548         u32     reg_3p0;                /* 0x120 */
 549         u32     reg_3p0_set;            /* 0x124 */
 550         u32     reg_3p0_clr;            /* 0x128 */
 551         u32     reg_3p0_tog;            /* 0x12c */
 552         u32     reg_2p5;                /* 0x130 */
 553         u32     reg_2p5_set;            /* 0x134 */
 554         u32     reg_2p5_clr;            /* 0x138 */
 555         u32     reg_2p5_tog;            /* 0x13c */
 556         u32     reg_core;               /* 0x140 */
 557         u32     reg_core_set;           /* 0x144 */
 558         u32     reg_core_clr;           /* 0x148 */
 559         u32     reg_core_tog;           /* 0x14c */
 560         u32     ana_misc0;              /* 0x150 */
 561         u32     ana_misc0_set;          /* 0x154 */
 562         u32     ana_misc0_clr;          /* 0x158 */
 563         u32     ana_misc0_tog;          /* 0x15c */
 564         u32     ana_misc1;              /* 0x160 */
 565         u32     ana_misc1_set;          /* 0x164 */
 566         u32     ana_misc1_clr;          /* 0x168 */
 567         u32     ana_misc1_tog;          /* 0x16c */
 568         u32     ana_misc2;              /* 0x170 */
 569         u32     ana_misc2_set;          /* 0x174 */
 570         u32     ana_misc2_clr;          /* 0x178 */
 571         u32     ana_misc2_tog;          /* 0x17c */
 572         u32     tempsense0;             /* 0x180 */
 573         u32     tempsense0_set;         /* 0x184 */
 574         u32     tempsense0_clr;         /* 0x188 */
 575         u32     tempsense0_tog;         /* 0x18c */
 576         u32     tempsense1;             /* 0x190 */
 577         u32     tempsense1_set;         /* 0x194 */
 578         u32     tempsense1_clr;         /* 0x198 */
 579         u32     tempsense1_tog;         /* 0x19c */
 580         u32     usb1_vbus_detect;       /* 0x1a0 */
 581         u32     usb1_vbus_detect_set;   /* 0x1a4 */
 582         u32     usb1_vbus_detect_clr;   /* 0x1a8 */
 583         u32     usb1_vbus_detect_tog;   /* 0x1ac */
 584         u32     usb1_chrg_detect;       /* 0x1b0 */
 585         u32     usb1_chrg_detect_set;   /* 0x1b4 */
 586         u32     usb1_chrg_detect_clr;   /* 0x1b8 */
 587         u32     usb1_chrg_detect_tog;   /* 0x1bc */
 588         u32     usb1_vbus_det_stat;     /* 0x1c0 */
 589         u32     usb1_vbus_det_stat_set; /* 0x1c4 */
 590         u32     usb1_vbus_det_stat_clr; /* 0x1c8 */
 591         u32     usb1_vbus_det_stat_tog; /* 0x1cc */
 592         u32     usb1_chrg_det_stat;     /* 0x1d0 */
 593         u32     usb1_chrg_det_stat_set; /* 0x1d4 */
 594         u32     usb1_chrg_det_stat_clr; /* 0x1d8 */
 595         u32     usb1_chrg_det_stat_tog; /* 0x1dc */
 596         u32     usb1_loopback;          /* 0x1e0 */
 597         u32     usb1_loopback_set;      /* 0x1e4 */
 598         u32     usb1_loopback_clr;      /* 0x1e8 */
 599         u32     usb1_loopback_tog;      /* 0x1ec */
 600         u32     usb1_misc;              /* 0x1f0 */
 601         u32     usb1_misc_set;          /* 0x1f4 */
 602         u32     usb1_misc_clr;          /* 0x1f8 */
 603         u32     usb1_misc_tog;          /* 0x1fc */
 604         u32     usb2_vbus_detect;       /* 0x200 */
 605         u32     usb2_vbus_detect_set;   /* 0x204 */
 606         u32     usb2_vbus_detect_clr;   /* 0x208 */
 607         u32     usb2_vbus_detect_tog;   /* 0x20c */
 608         u32     usb2_chrg_detect;       /* 0x210 */
 609         u32     usb2_chrg_detect_set;   /* 0x214 */
 610         u32     usb2_chrg_detect_clr;   /* 0x218 */
 611         u32     usb2_chrg_detect_tog;   /* 0x21c */
 612         u32     usb2_vbus_det_stat;     /* 0x220 */
 613         u32     usb2_vbus_det_stat_set; /* 0x224 */
 614         u32     usb2_vbus_det_stat_clr; /* 0x228 */
 615         u32     usb2_vbus_det_stat_tog; /* 0x22c */
 616         u32     usb2_chrg_det_stat;     /* 0x230 */
 617         u32     usb2_chrg_det_stat_set; /* 0x234 */
 618         u32     usb2_chrg_det_stat_clr; /* 0x238 */
 619         u32     usb2_chrg_det_stat_tog; /* 0x23c */
 620         u32     usb2_loopback;          /* 0x240 */
 621         u32     usb2_loopback_set;      /* 0x244 */
 622         u32     usb2_loopback_clr;      /* 0x248 */
 623         u32     usb2_loopback_tog;      /* 0x24c */
 624         u32     usb2_misc;              /* 0x250 */
 625         u32     usb2_misc_set;          /* 0x254 */
 626         u32     usb2_misc_clr;          /* 0x258 */
 627         u32     usb2_misc_tog;          /* 0x25c */
 628         u32     digprog;                /* 0x260 */
 629         u32     reserved1[7];
 630         u32     digprog_sololite;       /* 0x280 */
 631 };
 632
 633 #define ANATOP_PFD_480_PFD0_FRAC_SHIFT          0
 634 #define ANATOP_PFD_480_PFD0_FRAC_MASK           (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
 635 #define ANATOP_PFD_480_PFD0_STABLE_SHIFT        6
 636 #define ANATOP_PFD_480_PFD0_STABLE_MASK         (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
 637 #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT       7
 638 #define ANATOP_PFD_480_PFD0_CLKGATE_MASK        (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
 639 #define ANATOP_PFD_480_PFD1_FRAC_SHIFT          8
 640 #define ANATOP_PFD_480_PFD1_FRAC_MASK           (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
 641 #define ANATOP_PFD_480_PFD1_STABLE_SHIFT        14
 642 #define ANATOP_PFD_480_PFD1_STABLE_MASK         (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
 643 #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT       15
 644 #define ANATOP_PFD_480_PFD1_CLKGATE_MASK        (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
 645 #define ANATOP_PFD_480_PFD2_FRAC_SHIFT          16
 646 #define ANATOP_PFD_480_PFD2_FRAC_MASK           (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
 647 #define ANATOP_PFD_480_PFD2_STABLE_SHIFT        22
 648 #define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
 649 #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT       23
 650 #define ANATOP_PFD_480_PFD2_CLKGATE_MASK        (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
 651 #define ANATOP_PFD_480_PFD3_FRAC_SHIFT          24
 652 #define ANATOP_PFD_480_PFD3_FRAC_MASK           (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
 653 #define ANATOP_PFD_480_PFD3_STABLE_SHIFT        30
 654 #define ANATOP_PFD_480_PFD3_STABLE_MASK         (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
 655 #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT       31
 656
 657 struct iomuxc_base_regs {
 658         u32     gpr[14];        /* 0x000 */
 659         u32     obsrv[5];       /* 0x038 */
 660         u32     swmux_ctl[197]; /* 0x04c */
 661         u32     swpad_ctl[250]; /* 0x360 */
 662         u32     swgrp[26];      /* 0x748 */
 663         u32     daisy[104];     /* 0x7b0..94c */
 664 };
 665
 666 struct wdog_regs {
 667         u16     wcr;    /* Control */
 668         u16     wsr;    /* Service */
 669         u16     wrsr;   /* Reset Status */
 670         u16     wicr;   /* Interrupt Control */
 671         u16     wmcr;   /* Miscellaneous Control */
 672 };
 673
 674 #endif /* __ASSEMBLER__*/
 675 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */