2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
10 #include <asm/imx-common/regs-common.h>
14 #define ROMCP_ARB_BASE_ADDR 0x00000000
15 #define ROMCP_ARB_END_ADDR 0x000FFFFF
18 #define GPU_2D_ARB_BASE_ADDR 0x02200000
19 #define GPU_2D_ARB_END_ADDR 0x02203FFF
20 #define OPENVG_ARB_BASE_ADDR 0x02204000
21 #define OPENVG_ARB_END_ADDR 0x02207FFF
23 #define CAAM_ARB_BASE_ADDR 0x00100000
24 #define CAAM_ARB_END_ADDR 0x00103FFF
25 #define APBH_DMA_ARB_BASE_ADDR 0x00110000
26 #define APBH_DMA_ARB_END_ADDR 0x00117FFF
27 #define HDMI_ARB_BASE_ADDR 0x00120000
28 #define HDMI_ARB_END_ADDR 0x00128FFF
29 #define GPU_3D_ARB_BASE_ADDR 0x00130000
30 #define GPU_3D_ARB_END_ADDR 0x00133FFF
31 #define GPU_2D_ARB_BASE_ADDR 0x00134000
32 #define GPU_2D_ARB_END_ADDR 0x00137FFF
33 #define DTCP_ARB_BASE_ADDR 0x00138000
34 #define DTCP_ARB_END_ADDR 0x0013BFFF
35 #endif /* CONFIG_MX6SL */
37 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
38 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
39 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
41 /* GPV - PL301 configuration ports */
43 #define GPV2_BASE_ADDR 0x00D00000
45 #define GPV2_BASE_ADDR 0x00200000
48 #define GPV3_BASE_ADDR 0x00300000
49 #define GPV4_BASE_ADDR 0x00800000
50 #define IRAM_BASE_ADDR 0x00900000
51 #define SCU_BASE_ADDR 0x00A00000
52 #define IC_INTERFACES_BASE_ADDR 0x00A00100
53 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
54 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
55 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
56 #define GPV0_BASE_ADDR 0x00B00000
57 #define GPV1_BASE_ADDR 0x00C00000
58 #define PCIE_ARB_BASE_ADDR 0x01000000
59 #define PCIE_ARB_END_ADDR 0x01FFFFFF
61 #define AIPS1_ARB_BASE_ADDR 0x02000000
62 #define AIPS1_ARB_END_ADDR 0x020FFFFF
63 #define AIPS2_ARB_BASE_ADDR 0x02100000
64 #define AIPS2_ARB_END_ADDR 0x021FFFFF
65 #define SATA_ARB_BASE_ADDR 0x02200000
66 #define SATA_ARB_END_ADDR 0x02203FFF
67 #define OPENVG_ARB_BASE_ADDR 0x02204000
68 #define OPENVG_ARB_END_ADDR 0x02207FFF
69 #define HSI_ARB_BASE_ADDR 0x02208000
70 #define HSI_ARB_END_ADDR 0x0220BFFF
71 #define IPU1_ARB_BASE_ADDR 0x02400000
72 #define IPU1_ARB_END_ADDR 0x027FFFFF
73 #define IPU2_ARB_BASE_ADDR 0x02800000
74 #define IPU2_ARB_END_ADDR 0x02BFFFFF
75 #define WEIM_ARB_BASE_ADDR 0x08000000
76 #define WEIM_ARB_END_ADDR 0x0FFFFFFF
79 #define MMDC0_ARB_BASE_ADDR 0x80000000
80 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
81 #define MMDC1_ARB_BASE_ADDR 0xC0000000
82 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
84 #define MMDC0_ARB_BASE_ADDR 0x10000000
85 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
86 #define MMDC1_ARB_BASE_ADDR 0x80000000
87 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
90 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
91 #define IPU_SOC_OFFSET 0x00200000
93 /* Defines for Blocks connected via AIPS (SkyBlue) */
94 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
95 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
96 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
97 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
99 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
100 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
101 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
102 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
103 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
105 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
106 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
107 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
108 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
109 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
110 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
111 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
112 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
114 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
115 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
116 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
117 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
118 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
119 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
120 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
123 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
124 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
125 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
127 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
128 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
129 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
130 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
131 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
132 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
133 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
134 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
135 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
136 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
137 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
138 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
139 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
140 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
141 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
142 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
143 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
144 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
145 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
146 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
147 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
148 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
149 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
150 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
151 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
152 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
153 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
154 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
156 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
157 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
158 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
160 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
161 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
162 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
165 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
166 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
167 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
168 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
170 #define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
171 #define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
173 #define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
174 #define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
177 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
179 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
181 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
184 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
185 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
186 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
187 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
188 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
189 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
190 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
191 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
192 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
194 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
196 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
199 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
200 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
201 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
202 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
203 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
204 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
205 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
206 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
207 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
208 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
209 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
210 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
211 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
212 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
213 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
214 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
215 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
216 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
218 #define CHIP_REV_1_0 0x10
219 #define IRAM_SIZE 0x00040000
220 #define IMX_IIM_BASE OCOTP_BASE_ADDR
221 #define FEC_QUIRK_ENET_MAC
223 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
224 #include <asm/types.h>
226 /* System Reset Controller (SRC) */
248 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
249 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
250 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
251 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
252 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
253 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
254 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
255 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
256 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
257 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
258 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
259 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
260 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
261 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
262 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
263 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
264 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
265 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
266 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
267 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
268 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
269 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
270 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
271 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
272 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
273 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
274 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
275 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
277 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
278 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
279 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
280 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
282 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
283 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
285 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
286 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
288 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
289 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
291 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
292 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
298 /* mux and pad registers */
301 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
302 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
303 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
304 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
306 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
307 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
308 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
309 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
310 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
311 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
313 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
314 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
315 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
316 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
318 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
319 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
320 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
321 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
323 #define IOMUXC_GPR2_BITMAP_SPWG 0
324 #define IOMUXC_GPR2_BITMAP_JEIDA 1
326 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
327 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
328 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
329 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
331 #define IOMUXC_GPR2_DATA_WIDTH_18 0
332 #define IOMUXC_GPR2_DATA_WIDTH_24 1
334 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
335 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
336 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
337 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
339 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
340 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
341 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
342 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
344 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
345 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
346 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
347 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
349 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
350 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
352 #define IOMUXC_GPR2_MODE_DISABLED 0
353 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
354 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
356 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
357 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
358 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
359 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
360 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
362 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
363 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
364 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
365 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
366 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
368 /* ECSPI registers */
381 * CSPI register definitions
384 #define MXC_CSPICTRL_EN (1 << 0)
385 #define MXC_CSPICTRL_MODE (1 << 1)
386 #define MXC_CSPICTRL_XCH (1 << 2)
387 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
388 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
389 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
390 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
391 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
392 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
393 #define MXC_CSPICTRL_MAXBITS 0xfff
394 #define MXC_CSPICTRL_TC (1 << 7)
395 #define MXC_CSPICTRL_RXOVF (1 << 6)
396 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
397 #define MAX_SPI_BYTES 32
399 /* Bit position inside CTRL register to be associated with SS */
400 #define MXC_CSPICTRL_CHAN 18
402 /* Bit position inside CON register to be associated with SS */
403 #define MXC_CSPICON_POL 4
404 #define MXC_CSPICON_PHA 0
405 #define MXC_CSPICON_SSPOL 12
407 #define MXC_SPI_BASE_ADDRESSES \
413 #define MXC_SPI_BASE_ADDRESSES \
439 struct fuse_bank0_regs {
440 reg_32(misc_conf_lock);
450 struct fuse_bank4_regs {
451 reg_32(sjc_resp_low);
452 reg_32(sjc_resp_high);
453 reg_32(mac_addr_low);
454 reg_32(mac_addr_high);
468 struct iomuxc_base_regs {
469 u32 gpr[14]; /* 0x000 */
470 u32 obsrv[5]; /* 0x038 */
471 u32 swmux_ctl[197]; /* 0x04c */
472 u32 swpad_ctl[250]; /* 0x360 */
473 u32 swgrp[26]; /* 0x748 */
474 u32 daisy[104]; /* 0x7b0..94c */
478 u16 wcr; /* Control */
479 u16 wsr; /* Service */
480 u16 wrsr; /* Reset Status */
481 u16 wicr; /* Interrupt Control */
482 u16 wmcr; /* Miscellaneous Control */
485 #endif /* __ASSEMBLER__*/
487 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */