arch/arm/include/asm/arch-spear/spr_misc.h

   1 /*
   2  * (C) Copyright 2009
   3  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef _SPR_MISC_H
  25 #define _SPR_MISC_H
  26
  27 struct misc_regs {
  28         u32 auto_cfg_reg;       /* 0x0 */
  29         u32 armdbg_ctr_reg;     /* 0x4 */
  30         u32 pll1_cntl;          /* 0x8 */
  31         u32 pll1_frq;           /* 0xc */
  32         u32 pll1_mod;           /* 0x10 */
  33         u32 pll2_cntl;          /* 0x14 */
  34         u32 pll2_frq;           /* 0x18 */
  35         u32 pll2_mod;           /* 0x1C */
  36         u32 pll_ctr_reg;        /* 0x20 */
  37         u32 amba_clk_cfg;       /* 0x24 */
  38         u32 periph_clk_cfg;     /* 0x28 */
  39         u32 periph1_clken;      /* 0x2C */
  40         u32 soc_core_id;        /* 0x30 */
  41         u32 ras_clken;          /* 0x34 */
  42         u32 periph1_rst;        /* 0x38 */
  43         u32 periph2_rst;        /* 0x3C */
  44         u32 ras_rst;            /* 0x40 */
  45         u32 prsc1_clk_cfg;      /* 0x44 */
  46         u32 prsc2_clk_cfg;      /* 0x48 */
  47         u32 prsc3_clk_cfg;      /* 0x4C */
  48         u32 amem_cfg_ctrl;      /* 0x50 */
  49         u32 expi_clk_cfg;       /* 0x54 */
  50         u32 reserved_1;         /* 0x58 */
  51         u32 clcd_synth_clk;     /* 0x5C */
  52         u32 irda_synth_clk;     /* 0x60 */
  53         u32 uart_synth_clk;     /* 0x64 */
  54         u32 gmac_synth_clk;     /* 0x68 */
  55         u32 ras_synth1_clk;     /* 0x6C */
  56         u32 ras_synth2_clk;     /* 0x70 */
  57         u32 ras_synth3_clk;     /* 0x74 */
  58         u32 ras_synth4_clk;     /* 0x78 */
  59         u32 arb_icm_ml1;        /* 0x7C */
  60         u32 arb_icm_ml2;        /* 0x80 */
  61         u32 arb_icm_ml3;        /* 0x84 */
  62         u32 arb_icm_ml4;        /* 0x88 */
  63         u32 arb_icm_ml5;        /* 0x8C */
  64         u32 arb_icm_ml6;        /* 0x90 */
  65         u32 arb_icm_ml7;        /* 0x94 */
  66         u32 arb_icm_ml8;        /* 0x98 */
  67         u32 arb_icm_ml9;        /* 0x9C */
  68         u32 dma_src_sel;        /* 0xA0 */
  69         u32 uphy_ctr_reg;       /* 0xA4 */
  70         u32 gmac_ctr_reg;       /* 0xA8 */
  71         u32 port_bridge_ctrl;   /* 0xAC */
  72         u32 reserved_2[4];      /* 0xB0--0xBC */
  73         u32 prc1_ilck_ctrl_reg; /* 0xC0 */
  74         u32 prc2_ilck_ctrl_reg; /* 0xC4 */
  75         u32 prc3_ilck_ctrl_reg; /* 0xC8 */
  76         u32 prc4_ilck_ctrl_reg; /* 0xCC */
  77         u32 prc1_intr_ctrl_reg; /* 0xD0 */
  78         u32 prc2_intr_ctrl_reg; /* 0xD4 */
  79         u32 prc3_intr_ctrl_reg; /* 0xD8 */
  80         u32 prc4_intr_ctrl_reg; /* 0xDC */
  81         u32 powerdown_cfg_reg;  /* 0xE0 */
  82         u32 ddr_1v8_compensation;       /* 0xE4  */
  83         u32 ddr_2v5_compensation;       /* 0xE8 */
  84         u32 core_3v3_compensation;      /* 0xEC */
  85         u32 ddr_pad;            /* 0xF0 */
  86         u32 bist1_ctr_reg;      /* 0xF4 */
  87         u32 bist2_ctr_reg;      /* 0xF8 */
  88         u32 bist3_ctr_reg;      /* 0xFC */
  89         u32 bist4_ctr_reg;      /* 0x100 */
  90         u32 bist5_ctr_reg;      /* 0x104 */
  91         u32 bist1_rslt_reg;     /* 0x108 */
  92         u32 bist2_rslt_reg;     /* 0x10C */
  93         u32 bist3_rslt_reg;     /* 0x110 */
  94         u32 bist4_rslt_reg;     /* 0x114 */
  95         u32 bist5_rslt_reg;     /* 0x118 */
  96         u32 syst_error_reg;     /* 0x11C */
  97         u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */
  98         u32 ras_gpp1_in;        /* 0x8000 */
  99         u32 ras_gpp2_in;        /* 0x8004 */
 100         u32 ras_gpp1_out;       /* 0x8008 */
 101         u32 ras_gpp2_out;       /* 0x800C */
 102 };
 103
 104 /* SYNTH_CLK value*/
 105 #define SYNTH23                 0x00020003
 106
 107 /* PLLx_FRQ value */
 108 #if defined(CONFIG_SPEAR3XX)
 109 #define FREQ_332                0xA600010C
 110 #define FREQ_266                0x8500010C
 111 #elif defined(CONFIG_SPEAR600)
 112 #define FREQ_332                0xA600010F
 113 #define FREQ_266                0x8500010F
 114 #endif
 115
 116 /* PLL_CTR_REG   */
 117 #define MEM_CLK_SEL_MSK         0x70000000
 118 #define MEM_CLK_HCLK            0x00000000
 119 #define MEM_CLK_2HCLK           0x10000000
 120 #define MEM_CLK_PLL2            0x30000000
 121
 122 #define EXPI_CLK_CFG_LOW_COMPR  0x2000
 123 #define EXPI_CLK_CFG_CLK_EN     0x0400
 124 #define EXPI_CLK_CFG_RST        0x0200
 125 #define EXPI_CLK_SYNT_EN        0x0010
 126 #define EXPI_CLK_CFG_SEL_PLL2   0x0004
 127 #define EXPI_CLK_CFG_INT_CLK_EN 0x0001
 128
 129 #define PLL2_CNTL_6UA           0x1c00
 130 #define PLL2_CNTL_SAMPLE        0x0008
 131 #define PLL2_CNTL_ENABLE        0x0004
 132 #define PLL2_CNTL_RESETN        0x0002
 133 #define PLL2_CNTL_LOCK          0x0001
 134
 135 /* AUTO_CFG_REG value */
 136 #define MISC_SOCCFGMSK                  0x0000003F
 137 #define MISC_SOCCFG30                   0x0000000C
 138 #define MISC_SOCCFG31                   0x0000000D
 139 #define MISC_NANDDIS                    0x00020000
 140
 141 /* PERIPH_CLK_CFG value */
 142 #define MISC_GPT3SYNTH                  0x00000400
 143 #define MISC_GPT4SYNTH                  0x00000800
 144 #define CONFIG_SPEAR_UART48M            0
 145 #define CONFIG_SPEAR_UARTCLKMSK         (0x1 << 4)
 146
 147 /* PRSC_CLK_CFG value */
 148 /*
 149  * Fout = Fin / (2^(N+1) * (M + 1))
 150  */
 151 #define MISC_PRSC_N_1                   0x00001000
 152 #define MISC_PRSC_M_9                   0x00000009
 153 #define MISC_PRSC_N_4                   0x00004000
 154 #define MISC_PRSC_M_399                 0x0000018F
 155 #define MISC_PRSC_N_6                   0x00006000
 156 #define MISC_PRSC_M_2593                0x00000A21
 157 #define MISC_PRSC_M_124                 0x0000007C
 158 #define MISC_PRSC_CFG                   (MISC_PRSC_N_1 | MISC_PRSC_M_9)
 159
 160 /* PERIPH1_CLKEN, PERIPH1_RST value */
 161 #define MISC_USBDENB                    0x01000000
 162 #define MISC_ETHENB                     0x00800000
 163 #define MISC_SMIENB                     0x00200000
 164 #define MISC_GPT3ENB                    0x00010000
 165 #define MISC_GPIO4ENB                   0x00002000
 166 #define MISC_GPT2ENB                    0x00000800
 167 #define MISC_FSMCENB                    0x00000200
 168 #define MISC_I2CENB                     0x00000080
 169 #define MISC_SSP2ENB                    0x00000070
 170 #define MISC_UART0ENB                   0x00000008
 171
 172 /*   PERIPH_CLK_CFG   */
 173 #define  XTALTIMEEN             0x00000001
 174 #define  PLLTIMEEN              0x00000002
 175 #define  CLCDCLK_SYNTH          0x00000000
 176 #define  CLCDCLK_48MHZ          0x00000004
 177 #define  CLCDCLK_EXT            0x00000008
 178 #define  UARTCLK_MASK           (0x1 << 4)
 179 #define  UARTCLK_48MHZ          0x00000000
 180 #define  UARTCLK_SYNTH          0x00000010
 181 #define  IRDACLK_48MHZ          0x00000000
 182 #define  IRDACLK_SYNTH          0x00000020
 183 #define  IRDACLK_EXT            0x00000040
 184 #define  RTC_DISABLE            0x00000080
 185 #define  GPT1CLK_48MHZ          0x00000000
 186 #define  GPT1CLK_SYNTH          0x00000100
 187 #define  GPT2CLK_48MHZ          0x00000000
 188 #define  GPT2CLK_SYNTH          0x00000200
 189 #define  GPT3CLK_48MHZ          0x00000000
 190 #define  GPT3CLK_SYNTH          0x00000400
 191 #define  GPT4CLK_48MHZ          0x00000000
 192 #define  GPT4CLK_SYNTH          0x00000800
 193 #define  GPT5CLK_48MHZ          0x00000000
 194 #define  GPT5CLK_SYNTH          0x00001000
 195 #define  GPT1_FREEZE            0x00002000
 196 #define  GPT2_FREEZE            0x00004000
 197 #define  GPT3_FREEZE            0x00008000
 198 #define  GPT4_FREEZE            0x00010000
 199 #define  GPT5_FREEZE            0x00020000
 200
 201 /*  PERIPH1_CLKEN bits  */
 202 #define PERIPH_ARM1_WE          0x00000001
 203 #define PERIPH_ARM1             0x00000002
 204 #define PERIPH_ARM2             0x00000004
 205 #define PERIPH_UART1            0x00000008
 206 #define PERIPH_UART2            0x00000010
 207 #define PERIPH_SSP1             0x00000020
 208 #define PERIPH_SSP2             0x00000040
 209 #define PERIPH_I2C              0x00000080
 210 #define PERIPH_JPEG             0x00000100
 211 #define PERIPH_FSMC             0x00000200
 212 #define PERIPH_FIRDA            0x00000400
 213 #define PERIPH_GPT4             0x00000800
 214 #define PERIPH_GPT5             0x00001000
 215 #define PERIPH_GPIO4            0x00002000
 216 #define PERIPH_SSP3             0x00004000
 217 #define PERIPH_ADC              0x00008000
 218 #define PERIPH_GPT3             0x00010000
 219 #define PERIPH_RTC              0x00020000
 220 #define PERIPH_GPIO3            0x00040000
 221 #define PERIPH_DMA              0x00080000
 222 #define PERIPH_ROM              0x00100000
 223 #define PERIPH_SMI              0x00200000
 224 #define PERIPH_CLCD             0x00400000
 225 #define PERIPH_GMAC             0x00800000
 226 #define PERIPH_USBD             0x01000000
 227 #define PERIPH_USBH1            0x02000000
 228 #define PERIPH_USBH2            0x04000000
 229 #define PERIPH_MPMC             0x08000000
 230 #define PERIPH_RAMW             0x10000000
 231 #define PERIPH_MPMC_EN          0x20000000
 232 #define PERIPH_MPMC_WE          0x40000000
 233 #define PERIPH_MPMCMSK          0x60000000
 234
 235 #define PERIPH_CLK_ALL          0x0FFFFFF8
 236 #define PERIPH_RST_ALL          0x00000004
 237
 238 /* DDR_PAD values */
 239 #define DDR_PAD_CNF_MSK         0x0000ffff
 240 #define DDR_PAD_SW_CONF         0x00060000
 241 #define DDR_PAD_SSTL_SEL        0x00000001
 242 #define DDR_PAD_DRAM_TYPE       0x00008000
 243
 244 /* DDR_COMP values */
 245 #define DDR_COMP_ACCURATE       0x00000010
 246
 247 /* SoC revision stuff */
 248 #define SOC_PRI_SHFT            16
 249 #define SOC_SEC_SHFT            8
 250
 251 /* Revision definitions */
 252 #define SOC_SPEAR_NA            0
 253
 254 /*
 255  * The definitons have started from
 256  * 101 for SPEAr6xx
 257  * 201 for SPEAr3xx
 258  * 301 for SPEAr13xx
 259  */
 260 #define SOC_SPEAR600_AA         101
 261 #define SOC_SPEAR600_AB         102
 262 #define SOC_SPEAR600_BA         103
 263 #define SOC_SPEAR600_BB         104
 264 #define SOC_SPEAR600_BC         105
 265 #define SOC_SPEAR600_BD         106
 266
 267 #define SOC_SPEAR300            201
 268 #define SOC_SPEAR310            202
 269 #define SOC_SPEAR320            203
 270
 271 extern int get_socrev(void);
 272
 273 #endif