2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 /* Tegra2 clock control functions */
27 /* Set of oscillator frequencies supported in the internal API. */
29 /* All in MHz, so 13_0 is 13.0MHz */
38 /* The PLLs supported by the hardware */
41 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
48 /* now the simple ones */
49 CLOCK_ID_FIRST_SIMPLE,
50 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
54 /* These are the base clocks (inputs to the Tegra SOC) */
58 CLOCK_ID_COUNT, /* number of clocks */
62 /* The clocks supported by the hardware */
67 PERIPH_ID_CPU = PERIPH_ID_FIRST,
103 PERIPH_ID_RESERVED30,
106 /* Middle word: 63:32 */
110 PERIPH_ID_RESERVED35,
137 PERIPH_ID_RESERVED56,
146 /* Upper word 95:64 */
159 PERIPH_ID_RESERVED74,
161 PERIPH_ID_RESERVED76,
162 PERIPH_ID_RESERVED77,
163 PERIPH_ID_RESERVED78,
164 PERIPH_ID_RESERVED79,
167 PERIPH_ID_RESERVED80,
168 PERIPH_ID_RESERVED81,
169 PERIPH_ID_RESERVED82,
170 PERIPH_ID_RESERVED83,
183 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
184 #define PERIPH_REG(id) ((id) >> 5)
186 /* Mask value for a clock (within PERIPH_REG(id)) */
187 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
189 /* return 1 if a PLL ID is in range */
190 #define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
192 /* PLL stabilization delay in usec */
193 #define CLOCK_PLL_STABLE_DELAY_US 300
195 /* return the current oscillator clock frequency */
196 enum clock_osc_freq clock_get_osc_freq(void);
199 * Start PLL using the provided configuration parameters.
202 * @param divm input divider
203 * @param divn feedback divider
204 * @param divp post divider 2^n
205 * @param cpcon charge pump setup control
206 * @param lfcon loop filter setup control
208 * @returns monotonic time in us that the PLL will be stable
210 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
211 u32 divp, u32 cpcon, u32 lfcon);
218 void clock_enable(enum periph_id clkid);
225 void clock_disable(enum periph_id clkid);
228 * Set whether a clock is enabled or disabled.
231 * @param enable 1 to enable, 0 to disable
233 void clock_set_enable(enum periph_id clkid, int enable);
236 * Reset a peripheral. This puts it in reset, waits for a delay, then takes
237 * it out of reset and waits for th delay again.
239 * @param periph_id peripheral to reset
240 * @param us_delay time to delay in microseconds
242 void reset_periph(enum periph_id periph_id, int us_delay);
245 * Put a peripheral into or out of reset.
247 * @param periph_id peripheral to reset
248 * @param enable 1 to put into reset, 0 to take out of reset
250 void reset_set_enable(enum periph_id periph_id, int enable);
253 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
255 /* Things we can hold in reset for each CPU */
257 crc_rst_de = 1 << 2, /* What is de? */
258 crc_rst_watchdog = 1 << 3,
259 crc_rst_debug = 1 << 4,
263 * Put parts of the CPU complex into or out of reset.\
265 * @param cpu cpu number (0 or 1 on Tegra2)
266 * @param which which parts of the complex to affect (OR of crc_reset_id)
267 * @param reset 1 to assert reset, 0 to de-assert
269 void reset_cmplx_set_enable(int cpu, int which, int reset);
272 * Set the source for a peripheral clock. This plus the divisor sets the
273 * clock rate. You need to look up the datasheet to see the meaning of the
274 * source parameter as it changes for each peripheral.
276 * Warning: This function is only for use pre-relocation. Please use
277 * clock_start_periph_pll() instead.
279 * @param periph_id peripheral to adjust
280 * @param source source clock (0, 1, 2 or 3)
282 void clock_ll_set_source(enum periph_id periph_id, unsigned source);
285 * Set the source and divisor for a peripheral clock. This sets the
286 * clock rate. You need to look up the datasheet to see the meaning of the
287 * source parameter as it changes for each peripheral.
289 * Warning: This function is only for use pre-relocation. Please use
290 * clock_start_periph_pll() instead.
292 * @param periph_id peripheral to adjust
293 * @param source source clock (0, 1, 2 or 3)
294 * @param divisor divisor value to use
296 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
300 * Start a peripheral PLL clock at the given rate. This also resets the
303 * @param periph_id peripheral to start
304 * @param parent PLL id of required parent clock
305 * @param rate Required clock rate in Hz
306 * @return rate selected in Hz, or -1U if something went wrong
308 unsigned clock_start_periph_pll(enum periph_id periph_id,
309 enum clock_id parent, unsigned rate);
312 * Returns the rate of a peripheral clock in Hz. Since the caller almost
313 * certainly knows the parent clock (having just set it) we require that
314 * this be passed in so we don't need to work it out.
316 * @param periph_id peripheral to start
317 * @param parent PLL id of parent clock (used to calculate rate, you
319 * @return clock rate of peripheral in Hz
321 unsigned long clock_get_periph_rate(enum periph_id periph_id,
322 enum clock_id parent);
325 * Adjust peripheral PLL clock to the given rate. This does not reset the
326 * peripheral. If a second stage divisor is not available, pass NULL for
327 * extra_div. If it is available, then this parameter will return the
328 * divisor selected (which will be a power of 2 from 1 to 256).
330 * @param periph_id peripheral to start
331 * @param parent PLL id of required parent clock
332 * @param rate Required clock rate in Hz
333 * @param extra_div value for the second-stage divisor (NULL if one is
335 * @return rate selected in Hz, or -1U if something went wrong
337 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
338 enum clock_id parent, unsigned rate, int *extra_div);
341 * Returns the clock rate of a specified clock, in Hz.
343 * @param parent PLL id of clock to check
344 * @return rate of clock in Hz
346 unsigned clock_get_rate(enum clock_id clkid);
349 * Start up a UART using low-level calls
351 * Prior to relocation clock_start_periph_pll() cannot be called. This
352 * function provides a way to set up a UART using low-level calls which
353 * do not require BSS.
355 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
357 void clock_ll_start_uart(enum periph_id periph_id);
360 * Decode a peripheral ID from a device tree node.
362 * This works by looking up the peripheral's 'clocks' node and reading out
363 * the second cell, which is the clock number / peripheral ID.
365 * @param blob FDT blob to use
366 * @param node Node to look at
367 * @return peripheral ID, or PERIPH_ID_NONE if none
369 enum periph_id clock_decode_periph_id(const void *blob, int node);
372 * Checks that clocks are valid and prints a warning if not
374 * @return 0 if ok, -1 on error
376 int clock_verify(void);
378 /* Initialize the clocks */
379 void clock_init(void);
381 /* Initialize the PLLs */
382 void clock_early_init(void);