2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 /* Tegra2 clock control functions */
27 /* Set of oscillator frequencies supported in the internal API. */
29 /* All in MHz, so 13_0 is 13.0MHz */
38 /* The PLLs supported by the hardware */
41 CLOCK_PLL_ID_CGENERAL = CLOCK_PLL_ID_FIRST,
48 /* now the simple ones */
49 CLOCK_PLL_ID_FIRST_SIMPLE,
50 CLOCK_PLL_ID_XCPU = CLOCK_PLL_ID_FIRST_SIMPLE,
52 CLOCK_PLL_ID_SFROM32KHZ,
57 /* The clocks supported by the hardware */
62 PERIPH_ID_CPU = PERIPH_ID_FIRST,
101 /* Middle word: 63:32 */
105 PERIPH_ID_RESERVED35,
132 PERIPH_ID_RESERVED56,
141 /* Upper word 95:64 */
154 PERIPH_ID_RESERVED74,
156 PERIPH_ID_RESERVED76,
157 PERIPH_ID_RESERVED77,
158 PERIPH_ID_RESERVED78,
159 PERIPH_ID_RESERVED79,
162 PERIPH_ID_RESERVED80,
163 PERIPH_ID_RESERVED81,
164 PERIPH_ID_RESERVED82,
165 PERIPH_ID_RESERVED83,
177 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
178 #define PERIPH_REG(id) ((id) >> 5)
180 /* Mask value for a clock (within PERIPH_REG(id)) */
181 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
183 /* return 1 if a PLL ID is in range */
184 #define clock_pll_id_isvalid(id) ((id) >= CLOCK_PLL_ID_FIRST && \
185 (id) < CLOCK_PLL_ID_COUNT)
187 /* return 1 if a peripheral ID is in range */
188 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
189 (id) < PERIPH_ID_COUNT)
191 /* PLL stabilization delay in usec */
192 #define CLOCK_PLL_STABLE_DELAY_US 300
194 /* return the current oscillator clock frequency */
195 enum clock_osc_freq clock_get_osc_freq(void);
198 * Start PLL using the provided configuration parameters.
201 * @param divm input divider
202 * @param divn feedback divider
203 * @param divp post divider 2^n
204 * @param cpcon charge pump setup control
205 * @param lfcon loop filter setup control
207 * @returns monotonic time in us that the PLL will be stable
209 unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn,
210 u32 divp, u32 cpcon, u32 lfcon);
217 void clock_enable(enum periph_id clkid);
220 * Set whether a clock is enabled or disabled.
223 * @param enable 1 to enable, 0 to disable
225 void clock_set_enable(enum periph_id clkid, int enable);
228 * Reset a peripheral. This puts it in reset, waits for a delay, then takes
229 * it out of reset and waits for th delay again.
231 * @param periph_id peripheral to reset
232 * @param us_delay time to delay in microseconds
234 void reset_periph(enum periph_id periph_id, int us_delay);
237 * Put a peripheral into or out of reset.
239 * @param periph_id peripheral to reset
240 * @param enable 1 to put into reset, 0 to take out of reset
242 void reset_set_enable(enum periph_id periph_id, int enable);
245 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
247 /* Things we can hold in reset for each CPU */
249 crc_rst_de = 1 << 2, /* What is de? */
250 crc_rst_watchdog = 1 << 3,
251 crc_rst_debug = 1 << 4,
255 * Put parts of the CPU complex into or out of reset.\
257 * @param cpu cpu number (0 or 1 on Tegra2)
258 * @param which which parts of the complex to affect (OR of crc_reset_id)
259 * @param reset 1 to assert reset, 0 to de-assert
261 void reset_cmplx_set_enable(int cpu, int which, int reset);