2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #ifndef _TEGRA30_PINMUX_H_
18 #define _TEGRA30_PINMUX_H_
21 * Pin groups which we adjust. There are three basic attributes of each pin
22 * group which use this enum:
26 * - tristate or normal
29 PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
267 PINGRP_PEX_L0_PRSNT_N,
269 PINGRP_PEX_L0_CLKREQ_N,
271 PINGRP_PEX_L1_PRSNT_N,
273 PINGRP_PEX_L1_CLKREQ_N,
274 PINGRP_PEX_L2_PRSNT_N,
276 PINGRP_PEX_L2_CLKREQ_N,
277 PINGRP_HDMI_CEC, /* offset 0x33e0 */
282 PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
289 PDRIVE_PINGROUP_CDEV1,
290 PDRIVE_PINGROUP_CDEV2,
291 PDRIVE_PINGROUP_CSUS,
292 PDRIVE_PINGROUP_DAP1,
293 PDRIVE_PINGROUP_DAP2,
294 PDRIVE_PINGROUP_DAP3,
295 PDRIVE_PINGROUP_DAP4,
297 PDRIVE_PINGROUP_LCD1,
298 PDRIVE_PINGROUP_LCD2,
299 PDRIVE_PINGROUP_SDIO2,
300 PDRIVE_PINGROUP_SDIO3,
304 PDRIVE_PINGROUP_UART2,
305 PDRIVE_PINGROUP_UART3,
306 PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
307 PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
308 PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
321 PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
322 PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
323 PDRIVE_PINGROUP_COUNT,
327 * Functions which can be assigned to each of the pin groups. The values here
328 * bear no relation to the values programmed into pinmux registers and are
329 * purely a convenience. The translation is done through a table search.
334 PMUX_FUNC_AUDIO_SYNC,
343 PMUX_FUNC_EMC_TEST0_DLL,
344 PMUX_FUNC_EMC_TEST1_DLL,
390 PMUX_FUNC_VI_SENSOR_CLK,
404 PMUX_FUNC_EXTPERIPH1,
405 PMUX_FUNC_EXTPERIPH2,
406 PMUX_FUNC_EXTPERIPH3,
435 PMUX_FUNC_CLK_12M_OUT,
438 PMUX_FUNC_CORE_PWR_REQ,
439 PMUX_FUNC_CPU_PWR_REQ,
441 PMUX_FUNC_CLK_32K_IN,
446 PMUX_FUNC_RSVD1 = 0x8000,
447 PMUX_FUNC_RSVD2 = 0x8001,
448 PMUX_FUNC_RSVD3 = 0x8002,
449 PMUX_FUNC_RSVD4 = 0x8003,
452 /* return 1 if a pmux_func is in range */
453 #define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
454 || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
456 /* return 1 if a pingrp is in range */
457 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
459 /* The pullup/pulldown state of a pin group */
461 PMUX_PULL_NORMAL = 0,
465 /* return 1 if a pin_pupd_is in range */
466 #define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
467 ((pupd) <= PMUX_PULL_UP))
469 /* Defines whether a pin group is tristated or in normal operation */
472 PMUX_TRI_TRISTATE = 1,
474 /* return 1 if a pin_tristate_is in range */
475 #define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
476 && ((tristate) <= PMUX_TRI_TRISTATE))
482 /* return 1 if a pin_io_is in range */
483 #define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
484 ((io) <= PMUX_PIN_INPUT))
487 PMUX_PIN_LOCK_DEFAULT = 0,
488 PMUX_PIN_LOCK_DISABLE,
489 PMUX_PIN_LOCK_ENABLE,
491 /* return 1 if a pin_lock is in range */
492 #define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
493 ((lock) <= PMUX_PIN_LOCK_ENABLE))
496 PMUX_PIN_OD_DEFAULT = 0,
500 /* return 1 if a pin_od is in range */
501 #define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
502 ((od) <= PMUX_PIN_OD_ENABLE))
504 enum pmux_pin_ioreset {
505 PMUX_PIN_IO_RESET_DEFAULT = 0,
506 PMUX_PIN_IO_RESET_DISABLE,
507 PMUX_PIN_IO_RESET_ENABLE,
509 /* return 1 if a pin_ioreset_is in range */
510 #define pmux_pin_ioreset_isvalid(ioreset) \
511 (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
512 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
514 /* Available power domains used by pin groups */
535 /* t30 pin drive group and pin mux registers */
536 #define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
537 #define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
538 PDRIVE_PINGROUP_COUNT)
539 struct pmux_tri_ctlr {
540 uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
541 uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
542 uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
543 uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
544 uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
545 uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
546 uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
548 uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
550 uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
551 uint pmt_reserved5[PMUX_OFFSET];
552 uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
556 * This defines the configuration for a pin, including the function assigned,
557 * pull up/down settings and tristate settings. Having set up one of these
558 * you can call pinmux_config_pingroup() to configure a pin in one step. Also
559 * available is pinmux_config_table() to configure a list of pins.
561 struct pingroup_config {
562 enum pmux_pingrp pingroup; /* pin group PINGRP_... */
563 enum pmux_func func; /* function to assign FUNC_... */
564 enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
565 enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
566 enum pmux_pin_io io; /* input or output PMUX_PIN_... */
567 enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
568 enum pmux_pin_od od; /* open-drain or push-pull driver */
569 enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
572 /* Set a pin group to tristate */
573 void pinmux_tristate_enable(enum pmux_pingrp pin);
575 /* Set a pin group to normal (non tristate) */
576 void pinmux_tristate_disable(enum pmux_pingrp pin);
578 /* Set the pull up/down feature for a pin group */
579 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
581 /* Set the mux function for a pin group */
582 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
584 /* Set the complete configuration for a pin group */
585 void pinmux_config_pingroup(struct pingroup_config *config);
587 /* Set a pin group to tristate or normal */
588 void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
590 /* Set a pin group as input or output */
591 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
594 * Configure a list of pin groups
596 * @param config List of config items
597 * @param len Number of config items in list
599 void pinmux_config_table(struct pingroup_config *config, int len);
601 /* Set a group of pins from a table */
602 void pinmux_init(void);
604 #endif /* _TEGRA30_PINMUX_H_ */