arch/arm/include/asm/omap_common.h

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Aneesh V <aneesh@ti.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25 #ifndef _OMAP_COMMON_H_
  26 #define _OMAP_COMMON_H_
  27
  28 #include <common.h>
  29
  30 #define NUM_SYS_CLKS    7
  31
  32 struct prcm_regs {
  33         /* cm1.ckgen */
  34         u32 cm_clksel_core;
  35         u32 cm_clksel_abe;
  36         u32 cm_dll_ctrl;
  37         u32 cm_clkmode_dpll_core;
  38         u32 cm_idlest_dpll_core;
  39         u32 cm_autoidle_dpll_core;
  40         u32 cm_clksel_dpll_core;
  41         u32 cm_div_m2_dpll_core;
  42         u32 cm_div_m3_dpll_core;
  43         u32 cm_div_h11_dpll_core;
  44         u32 cm_div_h12_dpll_core;
  45         u32 cm_div_h13_dpll_core;
  46         u32 cm_div_h14_dpll_core;
  47         u32 cm_ssc_deltamstep_dpll_core;
  48         u32 cm_ssc_modfreqdiv_dpll_core;
  49         u32 cm_emu_override_dpll_core;
  50         u32 cm_div_h22_dpllcore;
  51         u32 cm_div_h23_dpll_core;
  52         u32 cm_clkmode_dpll_mpu;
  53         u32 cm_idlest_dpll_mpu;
  54         u32 cm_autoidle_dpll_mpu;
  55         u32 cm_clksel_dpll_mpu;
  56         u32 cm_div_m2_dpll_mpu;
  57         u32 cm_ssc_deltamstep_dpll_mpu;
  58         u32 cm_ssc_modfreqdiv_dpll_mpu;
  59         u32 cm_bypclk_dpll_mpu;
  60         u32 cm_clkmode_dpll_iva;
  61         u32 cm_idlest_dpll_iva;
  62         u32 cm_autoidle_dpll_iva;
  63         u32 cm_clksel_dpll_iva;
  64         u32 cm_div_h11_dpll_iva;
  65         u32 cm_div_h12_dpll_iva;
  66         u32 cm_ssc_deltamstep_dpll_iva;
  67         u32 cm_ssc_modfreqdiv_dpll_iva;
  68         u32 cm_bypclk_dpll_iva;
  69         u32 cm_clkmode_dpll_abe;
  70         u32 cm_idlest_dpll_abe;
  71         u32 cm_autoidle_dpll_abe;
  72         u32 cm_clksel_dpll_abe;
  73         u32 cm_div_m2_dpll_abe;
  74         u32 cm_div_m3_dpll_abe;
  75         u32 cm_ssc_deltamstep_dpll_abe;
  76         u32 cm_ssc_modfreqdiv_dpll_abe;
  77         u32 cm_clkmode_dpll_ddrphy;
  78         u32 cm_idlest_dpll_ddrphy;
  79         u32 cm_autoidle_dpll_ddrphy;
  80         u32 cm_clksel_dpll_ddrphy;
  81         u32 cm_div_m2_dpll_ddrphy;
  82         u32 cm_div_h11_dpll_ddrphy;
  83         u32 cm_div_h12_dpll_ddrphy;
  84         u32 cm_div_h13_dpll_ddrphy;
  85         u32 cm_ssc_deltamstep_dpll_ddrphy;
  86         u32 cm_shadow_freq_config1;
  87         u32 cm_mpu_mpu_clkctrl;
  88
  89         /* cm1.dsp */
  90         u32 cm_dsp_clkstctrl;
  91         u32 cm_dsp_dsp_clkctrl;
  92
  93         /* cm1.abe */
  94         u32 cm1_abe_clkstctrl;
  95         u32 cm1_abe_l4abe_clkctrl;
  96         u32 cm1_abe_aess_clkctrl;
  97         u32 cm1_abe_pdm_clkctrl;
  98         u32 cm1_abe_dmic_clkctrl;
  99         u32 cm1_abe_mcasp_clkctrl;
 100         u32 cm1_abe_mcbsp1_clkctrl;
 101         u32 cm1_abe_mcbsp2_clkctrl;
 102         u32 cm1_abe_mcbsp3_clkctrl;
 103         u32 cm1_abe_slimbus_clkctrl;
 104         u32 cm1_abe_timer5_clkctrl;
 105         u32 cm1_abe_timer6_clkctrl;
 106         u32 cm1_abe_timer7_clkctrl;
 107         u32 cm1_abe_timer8_clkctrl;
 108         u32 cm1_abe_wdt3_clkctrl;
 109
 110         /* cm2.ckgen */
 111         u32 cm_clksel_mpu_m3_iss_root;
 112         u32 cm_clksel_usb_60mhz;
 113         u32 cm_scale_fclk;
 114         u32 cm_core_dvfs_perf1;
 115         u32 cm_core_dvfs_perf2;
 116         u32 cm_core_dvfs_perf3;
 117         u32 cm_core_dvfs_perf4;
 118         u32 cm_core_dvfs_current;
 119         u32 cm_iva_dvfs_perf_tesla;
 120         u32 cm_iva_dvfs_perf_ivahd;
 121         u32 cm_iva_dvfs_perf_abe;
 122         u32 cm_iva_dvfs_current;
 123         u32 cm_clkmode_dpll_per;
 124         u32 cm_idlest_dpll_per;
 125         u32 cm_autoidle_dpll_per;
 126         u32 cm_clksel_dpll_per;
 127         u32 cm_div_m2_dpll_per;
 128         u32 cm_div_m3_dpll_per;
 129         u32 cm_div_h11_dpll_per;
 130         u32 cm_div_h12_dpll_per;
 131         u32 cm_div_h14_dpll_per;
 132         u32 cm_ssc_deltamstep_dpll_per;
 133         u32 cm_ssc_modfreqdiv_dpll_per;
 134         u32 cm_emu_override_dpll_per;
 135         u32 cm_clkmode_dpll_usb;
 136         u32 cm_idlest_dpll_usb;
 137         u32 cm_autoidle_dpll_usb;
 138         u32 cm_clksel_dpll_usb;
 139         u32 cm_div_m2_dpll_usb;
 140         u32 cm_ssc_deltamstep_dpll_usb;
 141         u32 cm_ssc_modfreqdiv_dpll_usb;
 142         u32 cm_clkdcoldo_dpll_usb;
 143         u32 cm_clkmode_dpll_unipro;
 144         u32 cm_idlest_dpll_unipro;
 145         u32 cm_autoidle_dpll_unipro;
 146         u32 cm_clksel_dpll_unipro;
 147         u32 cm_div_m2_dpll_unipro;
 148         u32 cm_ssc_deltamstep_dpll_unipro;
 149         u32 cm_ssc_modfreqdiv_dpll_unipro;
 150
 151         /* cm2.core */
 152         u32 cm_coreaon_bandgap_clkctrl;
 153         u32 cm_l3_1_clkstctrl;
 154         u32 cm_l3_1_dynamicdep;
 155         u32 cm_l3_1_l3_1_clkctrl;
 156         u32 cm_l3_2_clkstctrl;
 157         u32 cm_l3_2_dynamicdep;
 158         u32 cm_l3_2_l3_2_clkctrl;
 159         u32 cm_l3_2_gpmc_clkctrl;
 160         u32 cm_l3_2_ocmc_ram_clkctrl;
 161         u32 cm_mpu_m3_clkstctrl;
 162         u32 cm_mpu_m3_staticdep;
 163         u32 cm_mpu_m3_dynamicdep;
 164         u32 cm_mpu_m3_mpu_m3_clkctrl;
 165         u32 cm_sdma_clkstctrl;
 166         u32 cm_sdma_staticdep;
 167         u32 cm_sdma_dynamicdep;
 168         u32 cm_sdma_sdma_clkctrl;
 169         u32 cm_memif_clkstctrl;
 170         u32 cm_memif_dmm_clkctrl;
 171         u32 cm_memif_emif_fw_clkctrl;
 172         u32 cm_memif_emif_1_clkctrl;
 173         u32 cm_memif_emif_2_clkctrl;
 174         u32 cm_memif_dll_clkctrl;
 175         u32 cm_memif_emif_h1_clkctrl;
 176         u32 cm_memif_emif_h2_clkctrl;
 177         u32 cm_memif_dll_h_clkctrl;
 178         u32 cm_c2c_clkstctrl;
 179         u32 cm_c2c_staticdep;
 180         u32 cm_c2c_dynamicdep;
 181         u32 cm_c2c_sad2d_clkctrl;
 182         u32 cm_c2c_modem_icr_clkctrl;
 183         u32 cm_c2c_sad2d_fw_clkctrl;
 184         u32 cm_l4cfg_clkstctrl;
 185         u32 cm_l4cfg_dynamicdep;
 186         u32 cm_l4cfg_l4_cfg_clkctrl;
 187         u32 cm_l4cfg_hw_sem_clkctrl;
 188         u32 cm_l4cfg_mailbox_clkctrl;
 189         u32 cm_l4cfg_sar_rom_clkctrl;
 190         u32 cm_l3instr_clkstctrl;
 191         u32 cm_l3instr_l3_3_clkctrl;
 192         u32 cm_l3instr_l3_instr_clkctrl;
 193         u32 cm_l3instr_intrconn_wp1_clkctrl;
 194
 195         /* cm2.ivahd */
 196         u32 cm_ivahd_clkstctrl;
 197         u32 cm_ivahd_ivahd_clkctrl;
 198         u32 cm_ivahd_sl2_clkctrl;
 199
 200         /* cm2.cam */
 201         u32 cm_cam_clkstctrl;
 202         u32 cm_cam_iss_clkctrl;
 203         u32 cm_cam_fdif_clkctrl;
 204
 205         /* cm2.dss */
 206         u32 cm_dss_clkstctrl;
 207         u32 cm_dss_dss_clkctrl;
 208
 209         /* cm2.sgx */
 210         u32 cm_sgx_clkstctrl;
 211         u32 cm_sgx_sgx_clkctrl;
 212
 213         /* cm2.l3init */
 214         u32 cm_l3init_clkstctrl;
 215
 216         /* cm2.l3init */
 217         u32 cm_l3init_hsmmc1_clkctrl;
 218         u32 cm_l3init_hsmmc2_clkctrl;
 219         u32 cm_l3init_hsi_clkctrl;
 220         u32 cm_l3init_hsusbhost_clkctrl;
 221         u32 cm_l3init_hsusbotg_clkctrl;
 222         u32 cm_l3init_hsusbtll_clkctrl;
 223         u32 cm_l3init_p1500_clkctrl;
 224         u32 cm_l3init_fsusb_clkctrl;
 225         u32 cm_l3init_ocp2scp1_clkctrl;
 226
 227         /* cm2.l4per */
 228         u32 cm_l4per_clkstctrl;
 229         u32 cm_l4per_dynamicdep;
 230         u32 cm_l4per_adc_clkctrl;
 231         u32 cm_l4per_gptimer10_clkctrl;
 232         u32 cm_l4per_gptimer11_clkctrl;
 233         u32 cm_l4per_gptimer2_clkctrl;
 234         u32 cm_l4per_gptimer3_clkctrl;
 235         u32 cm_l4per_gptimer4_clkctrl;
 236         u32 cm_l4per_gptimer9_clkctrl;
 237         u32 cm_l4per_elm_clkctrl;
 238         u32 cm_l4per_gpio2_clkctrl;
 239         u32 cm_l4per_gpio3_clkctrl;
 240         u32 cm_l4per_gpio4_clkctrl;
 241         u32 cm_l4per_gpio5_clkctrl;
 242         u32 cm_l4per_gpio6_clkctrl;
 243         u32 cm_l4per_hdq1w_clkctrl;
 244         u32 cm_l4per_hecc1_clkctrl;
 245         u32 cm_l4per_hecc2_clkctrl;
 246         u32 cm_l4per_i2c1_clkctrl;
 247         u32 cm_l4per_i2c2_clkctrl;
 248         u32 cm_l4per_i2c3_clkctrl;
 249         u32 cm_l4per_i2c4_clkctrl;
 250         u32 cm_l4per_l4per_clkctrl;
 251         u32 cm_l4per_mcasp2_clkctrl;
 252         u32 cm_l4per_mcasp3_clkctrl;
 253         u32 cm_l4per_mgate_clkctrl;
 254         u32 cm_l4per_mcspi1_clkctrl;
 255         u32 cm_l4per_mcspi2_clkctrl;
 256         u32 cm_l4per_mcspi3_clkctrl;
 257         u32 cm_l4per_mcspi4_clkctrl;
 258         u32 cm_l4per_gpio7_clkctrl;
 259         u32 cm_l4per_gpio8_clkctrl;
 260         u32 cm_l4per_mmcsd3_clkctrl;
 261         u32 cm_l4per_mmcsd4_clkctrl;
 262         u32 cm_l4per_msprohg_clkctrl;
 263         u32 cm_l4per_slimbus2_clkctrl;
 264         u32 cm_l4per_uart1_clkctrl;
 265         u32 cm_l4per_uart2_clkctrl;
 266         u32 cm_l4per_uart3_clkctrl;
 267         u32 cm_l4per_uart4_clkctrl;
 268         u32 cm_l4per_mmcsd5_clkctrl;
 269         u32 cm_l4per_i2c5_clkctrl;
 270         u32 cm_l4per_uart5_clkctrl;
 271         u32 cm_l4per_uart6_clkctrl;
 272         u32 cm_l4sec_clkstctrl;
 273         u32 cm_l4sec_staticdep;
 274         u32 cm_l4sec_dynamicdep;
 275         u32 cm_l4sec_aes1_clkctrl;
 276         u32 cm_l4sec_aes2_clkctrl;
 277         u32 cm_l4sec_des3des_clkctrl;
 278         u32 cm_l4sec_pkaeip29_clkctrl;
 279         u32 cm_l4sec_rng_clkctrl;
 280         u32 cm_l4sec_sha2md51_clkctrl;
 281         u32 cm_l4sec_cryptodma_clkctrl;
 282
 283         /* l4 wkup regs */
 284         u32 cm_abe_pll_ref_clksel;
 285         u32 cm_sys_clksel;
 286         u32 cm_wkup_clkstctrl;
 287         u32 cm_wkup_l4wkup_clkctrl;
 288         u32 cm_wkup_wdtimer1_clkctrl;
 289         u32 cm_wkup_wdtimer2_clkctrl;
 290         u32 cm_wkup_gpio1_clkctrl;
 291         u32 cm_wkup_gptimer1_clkctrl;
 292         u32 cm_wkup_gptimer12_clkctrl;
 293         u32 cm_wkup_synctimer_clkctrl;
 294         u32 cm_wkup_usim_clkctrl;
 295         u32 cm_wkup_sarram_clkctrl;
 296         u32 cm_wkup_keyboard_clkctrl;
 297         u32 cm_wkup_rtc_clkctrl;
 298         u32 cm_wkup_bandgap_clkctrl;
 299         u32 cm_wkupaon_scrm_clkctrl;
 300         u32 prm_vc_val_bypass;
 301         u32 prm_vc_cfg_i2c_mode;
 302         u32 prm_vc_cfg_i2c_clk;
 303         u32 prm_sldo_core_setup;
 304         u32 prm_sldo_core_ctrl;
 305         u32 prm_sldo_mpu_setup;
 306         u32 prm_sldo_mpu_ctrl;
 307         u32 prm_sldo_mm_setup;
 308         u32 prm_sldo_mm_ctrl;
 309
 310         u32 cm_div_m4_dpll_core;
 311         u32 cm_div_m5_dpll_core;
 312         u32 cm_div_m6_dpll_core;
 313         u32 cm_div_m7_dpll_core;
 314         u32 cm_div_m4_dpll_iva;
 315         u32 cm_div_m5_dpll_iva;
 316         u32 cm_div_m4_dpll_ddrphy;
 317         u32 cm_div_m5_dpll_ddrphy;
 318         u32 cm_div_m6_dpll_ddrphy;
 319         u32 cm_div_m4_dpll_per;
 320         u32 cm_div_m5_dpll_per;
 321         u32 cm_div_m6_dpll_per;
 322         u32 cm_div_m7_dpll_per;
 323         u32 cm_l3instr_intrconn_wp1_clkct;
 324         u32 cm_l3init_usbphy_clkctrl;
 325         u32 cm_l4per_mcbsp4_clkctrl;
 326         u32 prm_vc_cfg_channel;
 327 };
 328
 329 struct omap_sys_ctrl_regs {
 330         u32 control_status;
 331         u32 control_id_code;
 332         u32 control_std_fuse_opp_bgap;
 333         u32 control_ldosram_iva_voltage_ctrl;
 334         u32 control_ldosram_mpu_voltage_ctrl;
 335         u32 control_ldosram_core_voltage_ctrl;
 336         u32 control_paconf_global;
 337         u32 control_paconf_mode;
 338         u32 control_smart1io_padconf_0;
 339         u32 control_smart1io_padconf_1;
 340         u32 control_smart1io_padconf_2;
 341         u32 control_smart2io_padconf_0;
 342         u32 control_smart2io_padconf_1;
 343         u32 control_smart2io_padconf_2;
 344         u32 control_smart3io_padconf_0;
 345         u32 control_smart3io_padconf_1;
 346         u32 control_pbias;
 347         u32 control_i2c_0;
 348         u32 control_camera_rx;
 349         u32 control_hdmi_tx_phy;
 350         u32 control_uniportm;
 351         u32 control_dsiphy;
 352         u32 control_mcbsplp;
 353         u32 control_usb2phycore;
 354         u32 control_hdmi_1;
 355         u32 control_hsi;
 356         u32 control_ddr3ch1_0;
 357         u32 control_ddr3ch2_0;
 358         u32 control_ddrch1_0;
 359         u32 control_ddrch1_1;
 360         u32 control_ddrch2_0;
 361         u32 control_ddrch2_1;
 362         u32 control_lpddr2ch1_0;
 363         u32 control_lpddr2ch1_1;
 364         u32 control_ddrio_0;
 365         u32 control_ddrio_1;
 366         u32 control_ddrio_2;
 367         u32 control_lpddr2io1_0;
 368         u32 control_lpddr2io1_1;
 369         u32 control_lpddr2io1_2;
 370         u32 control_lpddr2io1_3;
 371         u32 control_lpddr2io2_0;
 372         u32 control_lpddr2io2_1;
 373         u32 control_lpddr2io2_2;
 374         u32 control_lpddr2io2_3;
 375         u32 control_hyst_1;
 376         u32 control_usbb_hsic_control;
 377         u32 control_c2c;
 378         u32 control_core_control_spare_rw;
 379         u32 control_core_control_spare_r;
 380         u32 control_core_control_spare_r_c0;
 381         u32 control_srcomp_north_side;
 382         u32 control_srcomp_south_side;
 383         u32 control_srcomp_east_side;
 384         u32 control_srcomp_west_side;
 385         u32 control_srcomp_code_latch;
 386         u32 control_pbiaslite;
 387         u32 control_port_emif1_sdram_config;
 388         u32 control_port_emif1_lpddr2_nvm_config;
 389         u32 control_port_emif2_sdram_config;
 390         u32 control_emif1_sdram_config_ext;
 391         u32 control_emif2_sdram_config_ext;
 392         u32 control_smart1nopmio_padconf_0;
 393         u32 control_smart1nopmio_padconf_1;
 394         u32 control_padconf_mode;
 395         u32 control_xtal_oscillator;
 396         u32 control_i2c_2;
 397         u32 control_ckobuffer;
 398         u32 control_wkup_control_spare_rw;
 399         u32 control_wkup_control_spare_r;
 400         u32 control_wkup_control_spare_r_c0;
 401         u32 control_srcomp_east_side_wkup;
 402         u32 control_efuse_1;
 403         u32 control_efuse_2;
 404         u32 control_efuse_3;
 405         u32 control_efuse_4;
 406         u32 control_efuse_5;
 407         u32 control_efuse_6;
 408         u32 control_efuse_7;
 409         u32 control_efuse_8;
 410         u32 control_efuse_9;
 411         u32 control_efuse_10;
 412         u32 control_efuse_11;
 413         u32 control_efuse_12;
 414         u32 control_efuse_13;
 415 };
 416
 417 struct dpll_params {
 418         u32 m;
 419         u32 n;
 420         s8 m2;
 421         s8 m3;
 422         s8 m4_h11;
 423         s8 m5_h12;
 424         s8 m6_h13;
 425         s8 m7_h14;
 426         s8 h22;
 427         s8 h23;
 428 };
 429
 430 struct dpll_regs {
 431         u32 cm_clkmode_dpll;
 432         u32 cm_idlest_dpll;
 433         u32 cm_autoidle_dpll;
 434         u32 cm_clksel_dpll;
 435         u32 cm_div_m2_dpll;
 436         u32 cm_div_m3_dpll;
 437         u32 cm_div_m4_h11_dpll;
 438         u32 cm_div_m5_h12_dpll;
 439         u32 cm_div_m6_h13_dpll;
 440         u32 cm_div_m7_h14_dpll;
 441         u32 reserved[3];
 442         u32 cm_div_h22_dpll;
 443         u32 cm_div_h23_dpll;
 444 };
 445
 446 struct dplls {
 447         const struct dpll_params *mpu;
 448         const struct dpll_params *core;
 449         const struct dpll_params *per;
 450         const struct dpll_params *abe;
 451         const struct dpll_params *iva;
 452         const struct dpll_params *usb;
 453 };
 454
 455 struct pmic_data {
 456         u32 base_offset;
 457         u32 step;
 458         u32 start_code;
 459         unsigned gpio;
 460         int gpio_en;
 461 };
 462
 463 struct volts {
 464         u32 value;
 465         u32 addr;
 466         struct pmic_data *pmic;
 467 };
 468
 469 struct vcores_data {
 470         struct volts mpu;
 471         struct volts core;
 472         struct volts mm;
 473 };
 474
 475 extern struct prcm_regs const **prcm;
 476 extern struct prcm_regs const omap5_es1_prcm;
 477 extern struct prcm_regs const omap4_prcm;
 478 extern struct dplls const **dplls_data;
 479 extern struct vcores_data const **omap_vcores;
 480 extern const u32 sys_clk_array[8];
 481 extern struct omap_sys_ctrl_regs const **ctrl;
 482 extern struct omap_sys_ctrl_regs const omap4_ctrl;
 483 extern struct omap_sys_ctrl_regs const omap5_ctrl;
 484
 485 void hw_data_init(void);
 486
 487 const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
 488 const struct dpll_params *get_core_dpll_params(struct dplls const *);
 489 const struct dpll_params *get_per_dpll_params(struct dplls const *);
 490 const struct dpll_params *get_iva_dpll_params(struct dplls const *);
 491 const struct dpll_params *get_usb_dpll_params(struct dplls const *);
 492 const struct dpll_params *get_abe_dpll_params(struct dplls const *);
 493
 494 void do_enable_clocks(u32 const *clk_domains,
 495                       u32 const *clk_modules_hw_auto,
 496                       u32 const *clk_modules_explicit_en,
 497                       u8 wait_for_enable);
 498
 499 void setup_post_dividers(u32 const base,
 500                         const struct dpll_params *params);
 501 u32 omap_ddr_clk(void);
 502 u32 get_sys_clk_index(void);
 503 void enable_basic_clocks(void);
 504 void enable_basic_uboot_clocks(void);
 505 void enable_non_essential_clocks(void);
 506 void scale_vcores(struct vcores_data const *);
 507 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 508 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
 509
 510 /* Max value for DPLL multiplier M */
 511 #define OMAP_DPLL_MAX_N 127
 512
 513 /* HW Init Context */
 514 #define OMAP_INIT_CONTEXT_SPL                   0
 515 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR        1
 516 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL       2
 517 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH        3
 518
 519 static inline u32 omap_revision(void)
 520 {
 521         extern u32 *const omap_si_rev;
 522         return *omap_si_rev;
 523 }
 524
 525 /*
 526  * silicon revisions.
 527  * Moving this to common, so that most of code can be moved to common,
 528  * directories.
 529  */
 530
 531 /* omap4 */
 532 #define OMAP4430_SILICON_ID_INVALID     0xFFFFFFFF
 533 #define OMAP4430_ES1_0  0x44300100
 534 #define OMAP4430_ES2_0  0x44300200
 535 #define OMAP4430_ES2_1  0x44300210
 536 #define OMAP4430_ES2_2  0x44300220
 537 #define OMAP4430_ES2_3  0x44300230
 538 #define OMAP4460_ES1_0  0x44600100
 539 #define OMAP4460_ES1_1  0x44600110
 540
 541 /* omap5 */
 542 #define OMAP5430_SILICON_ID_INVALID     0
 543 #define OMAP5430_ES1_0  0x54300100
 544 #define OMAP5432_ES1_0  0x54320100
 545 #endif /* _OMAP_COMMON_H_ */