arch/arm/include/asm/omap_common.h

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Aneesh V <aneesh@ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #ifndef _OMAP_COMMON_H_
  10 #define _OMAP_COMMON_H_
  11
  12 #ifndef __ASSEMBLY__
  13
  14 #include <common.h>
  15
  16 #define NUM_SYS_CLKS    7
  17
  18 struct prcm_regs {
  19         /* cm1.ckgen */
  20         u32 cm_clksel_core;
  21         u32 cm_clksel_abe;
  22         u32 cm_dll_ctrl;
  23         u32 cm_clkmode_dpll_core;
  24         u32 cm_idlest_dpll_core;
  25         u32 cm_autoidle_dpll_core;
  26         u32 cm_clksel_dpll_core;
  27         u32 cm_div_m2_dpll_core;
  28         u32 cm_div_m3_dpll_core;
  29         u32 cm_div_h11_dpll_core;
  30         u32 cm_div_h12_dpll_core;
  31         u32 cm_div_h13_dpll_core;
  32         u32 cm_div_h14_dpll_core;
  33         u32 cm_div_h21_dpll_core;
  34         u32 cm_div_h24_dpll_core;
  35         u32 cm_ssc_deltamstep_dpll_core;
  36         u32 cm_ssc_modfreqdiv_dpll_core;
  37         u32 cm_emu_override_dpll_core;
  38         u32 cm_div_h22_dpllcore;
  39         u32 cm_div_h23_dpll_core;
  40         u32 cm_clkmode_dpll_mpu;
  41         u32 cm_idlest_dpll_mpu;
  42         u32 cm_autoidle_dpll_mpu;
  43         u32 cm_clksel_dpll_mpu;
  44         u32 cm_div_m2_dpll_mpu;
  45         u32 cm_ssc_deltamstep_dpll_mpu;
  46         u32 cm_ssc_modfreqdiv_dpll_mpu;
  47         u32 cm_bypclk_dpll_mpu;
  48         u32 cm_clkmode_dpll_iva;
  49         u32 cm_idlest_dpll_iva;
  50         u32 cm_autoidle_dpll_iva;
  51         u32 cm_clksel_dpll_iva;
  52         u32 cm_div_h11_dpll_iva;
  53         u32 cm_div_h12_dpll_iva;
  54         u32 cm_ssc_deltamstep_dpll_iva;
  55         u32 cm_ssc_modfreqdiv_dpll_iva;
  56         u32 cm_bypclk_dpll_iva;
  57         u32 cm_clkmode_dpll_abe;
  58         u32 cm_idlest_dpll_abe;
  59         u32 cm_autoidle_dpll_abe;
  60         u32 cm_clksel_dpll_abe;
  61         u32 cm_div_m2_dpll_abe;
  62         u32 cm_div_m3_dpll_abe;
  63         u32 cm_ssc_deltamstep_dpll_abe;
  64         u32 cm_ssc_modfreqdiv_dpll_abe;
  65         u32 cm_clkmode_dpll_ddrphy;
  66         u32 cm_idlest_dpll_ddrphy;
  67         u32 cm_autoidle_dpll_ddrphy;
  68         u32 cm_clksel_dpll_ddrphy;
  69         u32 cm_div_m2_dpll_ddrphy;
  70         u32 cm_div_h11_dpll_ddrphy;
  71         u32 cm_div_h12_dpll_ddrphy;
  72         u32 cm_div_h13_dpll_ddrphy;
  73         u32 cm_ssc_deltamstep_dpll_ddrphy;
  74         u32 cm_clkmode_dpll_dsp;
  75         u32 cm_shadow_freq_config1;
  76         u32 cm_clkmode_dpll_gmac;
  77         u32 cm_mpu_mpu_clkctrl;
  78
  79         /* cm1.dsp */
  80         u32 cm_dsp_clkstctrl;
  81         u32 cm_dsp_dsp_clkctrl;
  82
  83         /* cm1.abe */
  84         u32 cm1_abe_clkstctrl;
  85         u32 cm1_abe_l4abe_clkctrl;
  86         u32 cm1_abe_aess_clkctrl;
  87         u32 cm1_abe_pdm_clkctrl;
  88         u32 cm1_abe_dmic_clkctrl;
  89         u32 cm1_abe_mcasp_clkctrl;
  90         u32 cm1_abe_mcbsp1_clkctrl;
  91         u32 cm1_abe_mcbsp2_clkctrl;
  92         u32 cm1_abe_mcbsp3_clkctrl;
  93         u32 cm1_abe_slimbus_clkctrl;
  94         u32 cm1_abe_timer5_clkctrl;
  95         u32 cm1_abe_timer6_clkctrl;
  96         u32 cm1_abe_timer7_clkctrl;
  97         u32 cm1_abe_timer8_clkctrl;
  98         u32 cm1_abe_wdt3_clkctrl;
  99
 100         /* cm2.ckgen */
 101         u32 cm_clksel_mpu_m3_iss_root;
 102         u32 cm_clksel_usb_60mhz;
 103         u32 cm_scale_fclk;
 104         u32 cm_core_dvfs_perf1;
 105         u32 cm_core_dvfs_perf2;
 106         u32 cm_core_dvfs_perf3;
 107         u32 cm_core_dvfs_perf4;
 108         u32 cm_core_dvfs_current;
 109         u32 cm_iva_dvfs_perf_tesla;
 110         u32 cm_iva_dvfs_perf_ivahd;
 111         u32 cm_iva_dvfs_perf_abe;
 112         u32 cm_iva_dvfs_current;
 113         u32 cm_clkmode_dpll_per;
 114         u32 cm_idlest_dpll_per;
 115         u32 cm_autoidle_dpll_per;
 116         u32 cm_clksel_dpll_per;
 117         u32 cm_div_m2_dpll_per;
 118         u32 cm_div_m3_dpll_per;
 119         u32 cm_div_h11_dpll_per;
 120         u32 cm_div_h12_dpll_per;
 121         u32 cm_div_h13_dpll_per;
 122         u32 cm_div_h14_dpll_per;
 123         u32 cm_ssc_deltamstep_dpll_per;
 124         u32 cm_ssc_modfreqdiv_dpll_per;
 125         u32 cm_emu_override_dpll_per;
 126         u32 cm_clkmode_dpll_usb;
 127         u32 cm_idlest_dpll_usb;
 128         u32 cm_autoidle_dpll_usb;
 129         u32 cm_clksel_dpll_usb;
 130         u32 cm_div_m2_dpll_usb;
 131         u32 cm_ssc_deltamstep_dpll_usb;
 132         u32 cm_ssc_modfreqdiv_dpll_usb;
 133         u32 cm_clkdcoldo_dpll_usb;
 134         u32 cm_clkmode_dpll_pcie_ref;
 135         u32 cm_clkmode_apll_pcie;
 136         u32 cm_idlest_apll_pcie;
 137         u32 cm_div_m2_apll_pcie;
 138         u32 cm_clkvcoldo_apll_pcie;
 139         u32 cm_clkmode_dpll_unipro;
 140         u32 cm_idlest_dpll_unipro;
 141         u32 cm_autoidle_dpll_unipro;
 142         u32 cm_clksel_dpll_unipro;
 143         u32 cm_div_m2_dpll_unipro;
 144         u32 cm_ssc_deltamstep_dpll_unipro;
 145         u32 cm_ssc_modfreqdiv_dpll_unipro;
 146         u32 cm_coreaon_usb_phy_core_clkctrl;
 147
 148         /* cm2.core */
 149         u32 cm_coreaon_bandgap_clkctrl;
 150         u32 cm_coreaon_io_srcomp_clkctrl;
 151         u32 cm_l3_1_clkstctrl;
 152         u32 cm_l3_1_dynamicdep;
 153         u32 cm_l3_1_l3_1_clkctrl;
 154         u32 cm_l3_2_clkstctrl;
 155         u32 cm_l3_2_dynamicdep;
 156         u32 cm_l3_2_l3_2_clkctrl;
 157         u32 cm_l3_gpmc_clkctrl;
 158         u32 cm_l3_2_ocmc_ram_clkctrl;
 159         u32 cm_mpu_m3_clkstctrl;
 160         u32 cm_mpu_m3_staticdep;
 161         u32 cm_mpu_m3_dynamicdep;
 162         u32 cm_mpu_m3_mpu_m3_clkctrl;
 163         u32 cm_sdma_clkstctrl;
 164         u32 cm_sdma_staticdep;
 165         u32 cm_sdma_dynamicdep;
 166         u32 cm_sdma_sdma_clkctrl;
 167         u32 cm_memif_clkstctrl;
 168         u32 cm_memif_dmm_clkctrl;
 169         u32 cm_memif_emif_fw_clkctrl;
 170         u32 cm_memif_emif_1_clkctrl;
 171         u32 cm_memif_emif_2_clkctrl;
 172         u32 cm_memif_dll_clkctrl;
 173         u32 cm_memif_emif_h1_clkctrl;
 174         u32 cm_memif_emif_h2_clkctrl;
 175         u32 cm_memif_dll_h_clkctrl;
 176         u32 cm_c2c_clkstctrl;
 177         u32 cm_c2c_staticdep;
 178         u32 cm_c2c_dynamicdep;
 179         u32 cm_c2c_sad2d_clkctrl;
 180         u32 cm_c2c_modem_icr_clkctrl;
 181         u32 cm_c2c_sad2d_fw_clkctrl;
 182         u32 cm_l4cfg_clkstctrl;
 183         u32 cm_l4cfg_dynamicdep;
 184         u32 cm_l4cfg_l4_cfg_clkctrl;
 185         u32 cm_l4cfg_hw_sem_clkctrl;
 186         u32 cm_l4cfg_mailbox_clkctrl;
 187         u32 cm_l4cfg_sar_rom_clkctrl;
 188         u32 cm_l3instr_clkstctrl;
 189         u32 cm_l3instr_l3_3_clkctrl;
 190         u32 cm_l3instr_l3_instr_clkctrl;
 191         u32 cm_l3instr_intrconn_wp1_clkctrl;
 192
 193         /* cm2.ivahd */
 194         u32 cm_ivahd_clkstctrl;
 195         u32 cm_ivahd_ivahd_clkctrl;
 196         u32 cm_ivahd_sl2_clkctrl;
 197
 198         /* cm2.cam */
 199         u32 cm_cam_clkstctrl;
 200         u32 cm_cam_iss_clkctrl;
 201         u32 cm_cam_fdif_clkctrl;
 202         u32 cm_cam_vip1_clkctrl;
 203         u32 cm_cam_vip2_clkctrl;
 204         u32 cm_cam_vip3_clkctrl;
 205         u32 cm_cam_lvdsrx_clkctrl;
 206         u32 cm_cam_csi1_clkctrl;
 207         u32 cm_cam_csi2_clkctrl;
 208
 209         /* cm2.dss */
 210         u32 cm_dss_clkstctrl;
 211         u32 cm_dss_dss_clkctrl;
 212
 213         /* cm2.sgx */
 214         u32 cm_sgx_clkstctrl;
 215         u32 cm_sgx_sgx_clkctrl;
 216
 217         /* cm2.l3init */
 218         u32 cm_l3init_clkstctrl;
 219
 220         /* cm2.l3init */
 221         u32 cm_l3init_hsmmc1_clkctrl;
 222         u32 cm_l3init_hsmmc2_clkctrl;
 223         u32 cm_l3init_hsi_clkctrl;
 224         u32 cm_l3init_hsusbhost_clkctrl;
 225         u32 cm_l3init_hsusbotg_clkctrl;
 226         u32 cm_l3init_hsusbtll_clkctrl;
 227         u32 cm_l3init_p1500_clkctrl;
 228         u32 cm_l3init_fsusb_clkctrl;
 229         u32 cm_l3init_ocp2scp1_clkctrl;
 230         u32 cm_l3init_ocp2scp3_clkctrl;
 231         u32 cm_l3init_usb_otg_ss_clkctrl;
 232
 233         u32 prm_irqstatus_mpu_2;
 234
 235         /* cm2.l4per */
 236         u32 cm_l4per_clkstctrl;
 237         u32 cm_l4per_dynamicdep;
 238         u32 cm_l4per_adc_clkctrl;
 239         u32 cm_l4per_gptimer10_clkctrl;
 240         u32 cm_l4per_gptimer11_clkctrl;
 241         u32 cm_l4per_gptimer2_clkctrl;
 242         u32 cm_l4per_gptimer3_clkctrl;
 243         u32 cm_l4per_gptimer4_clkctrl;
 244         u32 cm_l4per_gptimer9_clkctrl;
 245         u32 cm_l4per_elm_clkctrl;
 246         u32 cm_l4per_gpio2_clkctrl;
 247         u32 cm_l4per_gpio3_clkctrl;
 248         u32 cm_l4per_gpio4_clkctrl;
 249         u32 cm_l4per_gpio5_clkctrl;
 250         u32 cm_l4per_gpio6_clkctrl;
 251         u32 cm_l4per_hdq1w_clkctrl;
 252         u32 cm_l4per_hecc1_clkctrl;
 253         u32 cm_l4per_hecc2_clkctrl;
 254         u32 cm_l4per_i2c1_clkctrl;
 255         u32 cm_l4per_i2c2_clkctrl;
 256         u32 cm_l4per_i2c3_clkctrl;
 257         u32 cm_l4per_i2c4_clkctrl;
 258         u32 cm_l4per_l4per_clkctrl;
 259         u32 cm_l4per_mcasp2_clkctrl;
 260         u32 cm_l4per_mcasp3_clkctrl;
 261         u32 cm_l4per_mgate_clkctrl;
 262         u32 cm_l4per_mcspi1_clkctrl;
 263         u32 cm_l4per_mcspi2_clkctrl;
 264         u32 cm_l4per_mcspi3_clkctrl;
 265         u32 cm_l4per_mcspi4_clkctrl;
 266         u32 cm_l4per_gpio7_clkctrl;
 267         u32 cm_l4per_gpio8_clkctrl;
 268         u32 cm_l4per_mmcsd3_clkctrl;
 269         u32 cm_l4per_mmcsd4_clkctrl;
 270         u32 cm_l4per_msprohg_clkctrl;
 271         u32 cm_l4per_slimbus2_clkctrl;
 272         u32 cm_l4per_qspi_clkctrl;
 273         u32 cm_l4per_uart1_clkctrl;
 274         u32 cm_l4per_uart2_clkctrl;
 275         u32 cm_l4per_uart3_clkctrl;
 276         u32 cm_l4per_uart4_clkctrl;
 277         u32 cm_l4per_mmcsd5_clkctrl;
 278         u32 cm_l4per_i2c5_clkctrl;
 279         u32 cm_l4per_uart5_clkctrl;
 280         u32 cm_l4per_uart6_clkctrl;
 281         u32 cm_l4sec_clkstctrl;
 282         u32 cm_l4sec_staticdep;
 283         u32 cm_l4sec_dynamicdep;
 284         u32 cm_l4sec_aes1_clkctrl;
 285         u32 cm_l4sec_aes2_clkctrl;
 286         u32 cm_l4sec_des3des_clkctrl;
 287         u32 cm_l4sec_pkaeip29_clkctrl;
 288         u32 cm_l4sec_rng_clkctrl;
 289         u32 cm_l4sec_sha2md51_clkctrl;
 290         u32 cm_l4sec_cryptodma_clkctrl;
 291
 292         /* l4 wkup regs */
 293         u32 cm_abe_pll_ref_clksel;
 294         u32 cm_sys_clksel;
 295         u32 cm_abe_pll_sys_clksel;
 296         u32 cm_wkup_clkstctrl;
 297         u32 cm_wkup_l4wkup_clkctrl;
 298         u32 cm_wkup_wdtimer1_clkctrl;
 299         u32 cm_wkup_wdtimer2_clkctrl;
 300         u32 cm_wkup_gpio1_clkctrl;
 301         u32 cm_wkup_gptimer1_clkctrl;
 302         u32 cm_wkup_gptimer12_clkctrl;
 303         u32 cm_wkup_synctimer_clkctrl;
 304         u32 cm_wkup_usim_clkctrl;
 305         u32 cm_wkup_sarram_clkctrl;
 306         u32 cm_wkup_keyboard_clkctrl;
 307         u32 cm_wkup_rtc_clkctrl;
 308         u32 cm_wkup_bandgap_clkctrl;
 309         u32 cm_wkupaon_scrm_clkctrl;
 310         u32 cm_wkupaon_io_srcomp_clkctrl;
 311         u32 prm_rstctrl;
 312         u32 prm_rstst;
 313         u32 prm_rsttime;
 314         u32 prm_vc_val_bypass;
 315         u32 prm_vc_cfg_i2c_mode;
 316         u32 prm_vc_cfg_i2c_clk;
 317         u32 prm_abbldo_mpu_setup;
 318         u32 prm_abbldo_mpu_ctrl;
 319
 320         u32 cm_div_m4_dpll_core;
 321         u32 cm_div_m5_dpll_core;
 322         u32 cm_div_m6_dpll_core;
 323         u32 cm_div_m7_dpll_core;
 324         u32 cm_div_m4_dpll_iva;
 325         u32 cm_div_m5_dpll_iva;
 326         u32 cm_div_m4_dpll_ddrphy;
 327         u32 cm_div_m5_dpll_ddrphy;
 328         u32 cm_div_m6_dpll_ddrphy;
 329         u32 cm_div_m4_dpll_per;
 330         u32 cm_div_m5_dpll_per;
 331         u32 cm_div_m6_dpll_per;
 332         u32 cm_div_m7_dpll_per;
 333         u32 cm_l3instr_intrconn_wp1_clkct;
 334         u32 cm_l3init_usbphy_clkctrl;
 335         u32 cm_l4per_mcbsp4_clkctrl;
 336         u32 prm_vc_cfg_channel;
 337
 338         /* SCRM stuff, used by some boards */
 339         u32 scrm_auxclk0;
 340         u32 scrm_auxclk1;
 341
 342         /* GMAC Clk Ctrl */
 343         u32 cm_gmac_gmac_clkctrl;
 344         u32 cm_gmac_clkstctrl;
 345 };
 346
 347 struct omap_sys_ctrl_regs {
 348         u32 control_status;
 349         u32 control_core_mac_id_0_lo;
 350         u32 control_core_mac_id_0_hi;
 351         u32 control_core_mac_id_1_lo;
 352         u32 control_core_mac_id_1_hi;
 353         u32 control_std_fuse_opp_vdd_mpu_2;
 354         u32 control_phy_power_usb;
 355         u32 control_core_mmr_lock1;
 356         u32 control_core_mmr_lock2;
 357         u32 control_core_mmr_lock3;
 358         u32 control_core_mmr_lock4;
 359         u32 control_core_mmr_lock5;
 360         u32 control_core_control_io1;
 361         u32 control_core_control_io2;
 362         u32 control_id_code;
 363         u32 control_std_fuse_opp_bgap;
 364         u32 control_ldosram_iva_voltage_ctrl;
 365         u32 control_ldosram_mpu_voltage_ctrl;
 366         u32 control_ldosram_core_voltage_ctrl;
 367         u32 control_usbotghs_ctrl;
 368         u32 control_padconf_core_base;
 369         u32 control_paconf_global;
 370         u32 control_paconf_mode;
 371         u32 control_smart1io_padconf_0;
 372         u32 control_smart1io_padconf_1;
 373         u32 control_smart1io_padconf_2;
 374         u32 control_smart2io_padconf_0;
 375         u32 control_smart2io_padconf_1;
 376         u32 control_smart2io_padconf_2;
 377         u32 control_smart3io_padconf_0;
 378         u32 control_smart3io_padconf_1;
 379         u32 control_pbias;
 380         u32 control_i2c_0;
 381         u32 control_camera_rx;
 382         u32 control_hdmi_tx_phy;
 383         u32 control_uniportm;
 384         u32 control_dsiphy;
 385         u32 control_mcbsplp;
 386         u32 control_usb2phycore;
 387         u32 control_hdmi_1;
 388         u32 control_hsi;
 389         u32 control_ddr3ch1_0;
 390         u32 control_ddr3ch2_0;
 391         u32 control_ddrch1_0;
 392         u32 control_ddrch1_1;
 393         u32 control_ddrch2_0;
 394         u32 control_ddrch2_1;
 395         u32 control_lpddr2ch1_0;
 396         u32 control_lpddr2ch1_1;
 397         u32 control_ddrio_0;
 398         u32 control_ddrio_1;
 399         u32 control_ddrio_2;
 400         u32 control_ddr_control_ext_0;
 401         u32 control_lpddr2io1_0;
 402         u32 control_lpddr2io1_1;
 403         u32 control_lpddr2io1_2;
 404         u32 control_lpddr2io1_3;
 405         u32 control_lpddr2io2_0;
 406         u32 control_lpddr2io2_1;
 407         u32 control_lpddr2io2_2;
 408         u32 control_lpddr2io2_3;
 409         u32 control_hyst_1;
 410         u32 control_usbb_hsic_control;
 411         u32 control_c2c;
 412         u32 control_core_control_spare_rw;
 413         u32 control_core_control_spare_r;
 414         u32 control_core_control_spare_r_c0;
 415         u32 control_srcomp_north_side;
 416         u32 control_srcomp_south_side;
 417         u32 control_srcomp_east_side;
 418         u32 control_srcomp_west_side;
 419         u32 control_srcomp_code_latch;
 420         u32 control_pbiaslite;
 421         u32 control_port_emif1_sdram_config;
 422         u32 control_port_emif1_lpddr2_nvm_config;
 423         u32 control_port_emif2_sdram_config;
 424         u32 control_emif1_sdram_config_ext;
 425         u32 control_emif2_sdram_config_ext;
 426         u32 control_wkup_ldovbb_mpu_voltage_ctrl;
 427         u32 control_smart1nopmio_padconf_0;
 428         u32 control_smart1nopmio_padconf_1;
 429         u32 control_padconf_mode;
 430         u32 control_xtal_oscillator;
 431         u32 control_i2c_2;
 432         u32 control_ckobuffer;
 433         u32 control_wkup_control_spare_rw;
 434         u32 control_wkup_control_spare_r;
 435         u32 control_wkup_control_spare_r_c0;
 436         u32 control_srcomp_east_side_wkup;
 437         u32 control_efuse_1;
 438         u32 control_efuse_2;
 439         u32 control_efuse_3;
 440         u32 control_efuse_4;
 441         u32 control_efuse_5;
 442         u32 control_efuse_6;
 443         u32 control_efuse_7;
 444         u32 control_efuse_8;
 445         u32 control_efuse_9;
 446         u32 control_efuse_10;
 447         u32 control_efuse_11;
 448         u32 control_efuse_12;
 449         u32 control_efuse_13;
 450         u32 control_padconf_wkup_base;
 451 };
 452
 453 struct dpll_params {
 454         u32 m;
 455         u32 n;
 456         s8 m2;
 457         s8 m3;
 458         s8 m4_h11;
 459         s8 m5_h12;
 460         s8 m6_h13;
 461         s8 m7_h14;
 462         s8 h21;
 463         s8 h22;
 464         s8 h23;
 465         s8 h24;
 466 };
 467
 468 struct dpll_regs {
 469         u32 cm_clkmode_dpll;
 470         u32 cm_idlest_dpll;
 471         u32 cm_autoidle_dpll;
 472         u32 cm_clksel_dpll;
 473         u32 cm_div_m2_dpll;
 474         u32 cm_div_m3_dpll;
 475         u32 cm_div_m4_h11_dpll;
 476         u32 cm_div_m5_h12_dpll;
 477         u32 cm_div_m6_h13_dpll;
 478         u32 cm_div_m7_h14_dpll;
 479         u32 reserved[2];
 480         u32 cm_div_h21_dpll;
 481         u32 cm_div_h22_dpll;
 482         u32 cm_div_h23_dpll;
 483         u32 cm_div_h24_dpll;
 484 };
 485
 486 struct dplls {
 487         const struct dpll_params *mpu;
 488         const struct dpll_params *core;
 489         const struct dpll_params *per;
 490         const struct dpll_params *abe;
 491         const struct dpll_params *iva;
 492         const struct dpll_params *usb;
 493         const struct dpll_params *ddr;
 494         const struct dpll_params *gmac;
 495 };
 496
 497 struct pmic_data {
 498         u32 base_offset;
 499         u32 step;
 500         u32 start_code;
 501         unsigned gpio;
 502         int gpio_en;
 503         u32 i2c_slave_addr;
 504         void (*pmic_bus_init)(void);
 505         int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
 506 };
 507
 508 /**
 509  * struct volts_efuse_data - efuse definition for voltage
 510  * @reg:        register address for efuse
 511  * @reg_bits:   Number of bits in a register address, mandatory.
 512  */
 513 struct volts_efuse_data {
 514         u32 reg;
 515         u8 reg_bits;
 516 };
 517
 518 struct volts {
 519         u32 value;
 520         u32 addr;
 521         struct volts_efuse_data efuse;
 522         struct pmic_data *pmic;
 523 };
 524
 525 struct vcores_data {
 526         struct volts mpu;
 527         struct volts core;
 528         struct volts mm;
 529         struct volts gpu;
 530         struct volts eve;
 531         struct volts iva;
 532 };
 533
 534 extern struct prcm_regs const **prcm;
 535 extern struct prcm_regs const omap5_es1_prcm;
 536 extern struct prcm_regs const omap5_es2_prcm;
 537 extern struct prcm_regs const omap4_prcm;
 538 extern struct prcm_regs const dra7xx_prcm;
 539 extern struct dplls const **dplls_data;
 540 extern struct vcores_data const **omap_vcores;
 541 extern const u32 sys_clk_array[8];
 542 extern struct omap_sys_ctrl_regs const **ctrl;
 543 extern struct omap_sys_ctrl_regs const omap4_ctrl;
 544 extern struct omap_sys_ctrl_regs const omap5_ctrl;
 545 extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
 546
 547 void hw_data_init(void);
 548
 549 const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
 550 const struct dpll_params *get_core_dpll_params(struct dplls const *);
 551 const struct dpll_params *get_per_dpll_params(struct dplls const *);
 552 const struct dpll_params *get_iva_dpll_params(struct dplls const *);
 553 const struct dpll_params *get_usb_dpll_params(struct dplls const *);
 554 const struct dpll_params *get_abe_dpll_params(struct dplls const *);
 555
 556 void do_enable_clocks(u32 const *clk_domains,
 557                       u32 const *clk_modules_hw_auto,
 558                       u32 const *clk_modules_explicit_en,
 559                       u8 wait_for_enable);
 560
 561 void setup_post_dividers(u32 const base,
 562                         const struct dpll_params *params);
 563 u32 omap_ddr_clk(void);
 564 u32 get_sys_clk_index(void);
 565 void enable_basic_clocks(void);
 566 void enable_basic_uboot_clocks(void);
 567 void enable_non_essential_clocks(void);
 568 void scale_vcores(struct vcores_data const *);
 569 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 570 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
 571 void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
 572                u32 txdone, u32 txdone_mask, u32 opp);
 573 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 574
 575 /* HW Init Context */
 576 #define OMAP_INIT_CONTEXT_SPL                   0
 577 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR        1
 578 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL       2
 579 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH        3
 580
 581 /* ABB */
 582 #define OMAP_ABB_NOMINAL_OPP            0
 583 #define OMAP_ABB_FAST_OPP               1
 584 #define OMAP_ABB_SLOW_OPP               3
 585 #define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK              (0x1 << 0)
 586 #define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK              (0x1 << 1)
 587 #define OMAP_ABB_CONTROL_OPP_CHANGE_MASK                (0x1 << 2)
 588 #define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK         (0x1 << 6)
 589 #define OMAP_ABB_SETUP_SR2EN_MASK                       (0x1 << 0)
 590 #define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK              (0x1 << 2)
 591 #define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK              (0x1 << 1)
 592 #define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK             (0xff << 8)
 593
 594 static inline u32 omap_revision(void)
 595 {
 596         extern u32 *const omap_si_rev;
 597         return *omap_si_rev;
 598 }
 599
 600 #define OMAP54xx        0x54000000
 601
 602 static inline u8 is_omap54xx(void)
 603 {
 604         extern u32 *const omap_si_rev;
 605         return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
 606 }
 607 #endif
 608
 609 /*
 610  * silicon revisions.
 611  * Moving this to common, so that most of code can be moved to common,
 612  * directories.
 613  */
 614
 615 /* omap4 */
 616 #define OMAP4430_SILICON_ID_INVALID     0xFFFFFFFF
 617 #define OMAP4430_ES1_0  0x44300100
 618 #define OMAP4430_ES2_0  0x44300200
 619 #define OMAP4430_ES2_1  0x44300210
 620 #define OMAP4430_ES2_2  0x44300220
 621 #define OMAP4430_ES2_3  0x44300230
 622 #define OMAP4460_ES1_0  0x44600100
 623 #define OMAP4460_ES1_1  0x44600110
 624 #define OMAP4470_ES1_0  0x44700100
 625
 626 /* omap5 */
 627 #define OMAP5430_SILICON_ID_INVALID     0
 628 #define OMAP5430_ES1_0  0x54300100
 629 #define OMAP5432_ES1_0  0x54320100
 630 #define OMAP5430_ES2_0  0x54300200
 631 #define OMAP5432_ES2_0  0x54320200
 632
 633 /* DRA7XX */
 634 #define DRA752_ES1_0    0x07520100
 635
 636 /*
 637  * SRAM scratch space entries
 638  */
 639 #define OMAP_SRAM_SCRATCH_OMAP_REV      SRAM_SCRATCH_SPACE_ADDR
 640 #define OMAP_SRAM_SCRATCH_EMIF_SIZE     (SRAM_SCRATCH_SPACE_ADDR + 0x4)
 641 #define OMAP_SRAM_SCRATCH_EMIF_T_NUM    (SRAM_SCRATCH_SPACE_ADDR + 0xC)
 642 #define OMAP_SRAM_SCRATCH_EMIF_T_DEN    (SRAM_SCRATCH_SPACE_ADDR + 0x10)
 643 #define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
 644 #define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
 645 #define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
 646 #define OMAP_SRAM_SCRATCH_SYS_CTRL      (SRAM_SCRATCH_SPACE_ADDR + 0x20)
 647 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS   (SRAM_SCRATCH_SPACE_ADDR + 0x24)
 648 #define OMAP5_SRAM_SCRATCH_SPACE_END    (SRAM_SCRATCH_SPACE_ADDR + 0x28)
 649
 650 #endif /* _OMAP_COMMON_H_ */