arch/arm/mach-socfpga/reset_manager.c

   1 /*
   2  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/reset_manager.h>
  11 #include <asm/arch/fpga_manager.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 static const struct socfpga_reset_manager *reset_manager_base =
  16                 (void *)SOCFPGA_RSTMGR_ADDRESS;
  17
  18 /* Assert or de-assert SoCFPGA reset manager reset. */
  19 void socfpga_per_reset(u32 reset, int set)
  20 {
  21         const void *reg;
  22
  23         if (RSTMGR_BANK(reset) == 0)
  24                 reg = &reset_manager_base->mpu_mod_reset;
  25         else if (RSTMGR_BANK(reset) == 1)
  26                 reg = &reset_manager_base->per_mod_reset;
  27         else if (RSTMGR_BANK(reset) == 2)
  28                 reg = &reset_manager_base->per2_mod_reset;
  29         else if (RSTMGR_BANK(reset) == 3)
  30                 reg = &reset_manager_base->brg_mod_reset;
  31         else if (RSTMGR_BANK(reset) == 4)
  32                 reg = &reset_manager_base->misc_mod_reset;
  33         else    /* Invalid reset register, do nothing */
  34                 return;
  35
  36         if (set)
  37                 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
  38         else
  39                 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
  40 }
  41
  42 /*
  43  * Assert reset on every peripheral but L4WD0.
  44  * Watchdog must be kept intact to prevent glitches
  45  * and/or hangs.
  46  */
  47 void socfpga_per_reset_all(void)
  48 {
  49         const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
  50
  51         writel(~l4wd0, &reset_manager_base->per_mod_reset);
  52         writel(0xffffffff, &reset_manager_base->per2_mod_reset);
  53 }
  54
  55 /*
  56  * Write the reset manager register to cause reset
  57  */
  58 void reset_cpu(ulong addr)
  59 {
  60         /* request a warm reset */
  61         writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
  62                 &reset_manager_base->ctrl);
  63         /*
  64          * infinite loop here as watchdog will trigger and reset
  65          * the processor
  66          */
  67         while (1)
  68                 ;
  69 }
  70
  71 /*
  72  * Release peripherals from reset based on handoff
  73  */
  74 void reset_deassert_peripherals_handoff(void)
  75 {
  76         writel(0, &reset_manager_base->per_mod_reset);
  77 }
  78
  79 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  80 void socfpga_bridges_reset(int enable)
  81 {
  82         /* For SoCFPGA-VT, this is NOP. */
  83 }
  84 #else
  85
  86 #define L3REGS_REMAP_LWHPS2FPGA_MASK    0x10
  87 #define L3REGS_REMAP_HPS2FPGA_MASK      0x08
  88 #define L3REGS_REMAP_OCRAM_MASK         0x01
  89
  90 void socfpga_bridges_reset(int enable)
  91 {
  92         const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
  93                                 L3REGS_REMAP_HPS2FPGA_MASK |
  94                                 L3REGS_REMAP_OCRAM_MASK;
  95
  96         if (enable) {
  97                 /* brdmodrst */
  98                 writel(0xffffffff, &reset_manager_base->brg_mod_reset);
  99         } else {
 100                 /* Check signal from FPGA. */
 101                 if (!fpgamgr_test_fpga_ready()) {
 102                         /* FPGA not ready, do nothing. */
 103                         printf("%s: FPGA not ready, aborting.\n", __func__);
 104                         return;
 105                 }
 106
 107                 /* brdmodrst */
 108                 writel(0, &reset_manager_base->brg_mod_reset);
 109
 110                 /* Remap the bridges into memory map */
 111                 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
 112         }
 113 }
 114 #endif