2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <mach/sbc-regs.h>
10 #include <mach/sg-regs.h>
14 /* XECS0: boot/sub memory (boot swap = off/on) */
15 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
16 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
17 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
18 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
20 /* XECS1: sub/boot memory (boot swap = off/on) */
21 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
22 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
23 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
24 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
26 /* XECS3: peripherals */
27 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
28 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
29 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
30 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
32 writel(0x0000bc01, SBBASE0); /* boot memory */
33 writel(0x0400bc01, SBBASE1); /* sub memory */
34 writel(0x0800bf01, SBBASE3); /* peripherals */
36 /* enable access to sub memory when boot swap is on */
37 if (boot_is_swapped())
38 sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
40 sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
41 writel(0x00000001, SG_LOADPINCTRL);