arch/blackfin/cpu/cpu.c

   1 /*
   2  * U-boot - cpu.c CPU specific functions
   3  *
   4  * Copyright (c) 2005-2008 Analog Devices Inc.
   5  *
   6  * (C) Copyright 2000-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #include <common.h>
  13 #include <command.h>
  14 #include <asm/blackfin.h>
  15 #include <asm/cplb.h>
  16 #include <asm/mach-common/bits/core.h>
  17 #include <asm/mach-common/bits/ebiu.h>
  18 #include <asm/mach-common/bits/trace.h>
  19
  20 #include "cpu.h"
  21 #include "serial.h"
  22 #include "initcode.h"
  23
  24 ulong bfin_poweron_retx;
  25
  26 __attribute__ ((__noreturn__))
  27 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
  28 {
  29 #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
  30         /* Build a NOP slide over the LDR jump block.  Whee! */
  31         char nops[0xC];
  32         serial_early_puts("NOP Slide\n");
  33         memset(nops, 0x00, sizeof(nops));
  34         memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
  35 #endif
  36
  37         if (!loaded_from_ldr) {
  38                 /* Relocate sections into L1 if the LDR didn't do it -- don't
  39                  * check length because the linker script does the size
  40                  * checking at build time.
  41                  */
  42                 serial_early_puts("L1 Relocate\n");
  43                 extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
  44                 memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
  45                 extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
  46                 memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
  47         }
  48
  49         /*
  50          * Make sure our async settings are committed.  Some bootroms
  51          * (like the BF537) will reset some registers on us after it
  52          * has finished loading the LDR.  Or if we're booting over
  53          * JTAG, the initcode never got a chance to run.  Or if we
  54          * aren't booting from parallel flash, the initcode skipped
  55          * this step completely.
  56          */
  57         program_async_controller(NULL);
  58
  59         /* Save RETX so we can pass it while booting Linux */
  60         bfin_poweron_retx = bootflag;
  61
  62 #ifdef CONFIG_DEBUG_DUMP
  63         /* Turn on hardware trace buffer */
  64         bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
  65 #endif
  66
  67 #ifndef CONFIG_PANIC_HANG
  68         /* Reset upon a double exception rather than just hanging.
  69          * Do not do bfin_read on SWRST as that will reset status bits.
  70          */
  71 # ifdef SWRST
  72         bfin_write_SWRST(DOUBLE_FAULT);
  73 # endif
  74 #endif
  75
  76         serial_early_puts("Board init flash\n");
  77         board_init_f(bootflag);
  78 }
  79
  80 int exception_init(void)
  81 {
  82         bfin_write_EVT3(trap);
  83         return 0;
  84 }
  85
  86 int irq_init(void)
  87 {
  88 #ifdef SIC_IMASK0
  89         bfin_write_SIC_IMASK0(0);
  90         bfin_write_SIC_IMASK1(0);
  91 # ifdef SIC_IMASK2
  92         bfin_write_SIC_IMASK2(0);
  93 # endif
  94 #elif defined(SICA_IMASK0)
  95         bfin_write_SICA_IMASK0(0);
  96         bfin_write_SICA_IMASK1(0);
  97 #elif defined(SIC_IMASK)
  98         bfin_write_SIC_IMASK(0);
  99 #endif
 100         /* Set up a dummy NMI handler if needed.  */
 101         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
 102                 bfin_write_EVT2(evt_nmi);       /* NMI */
 103         bfin_write_EVT5(evt_default);   /* hardware error */
 104         bfin_write_EVT6(evt_default);   /* core timer */
 105         bfin_write_EVT7(evt_default);
 106         bfin_write_EVT8(evt_default);
 107         bfin_write_EVT9(evt_default);
 108         bfin_write_EVT10(evt_default);
 109         bfin_write_EVT11(evt_default);
 110         bfin_write_EVT12(evt_default);
 111         bfin_write_EVT13(evt_default);
 112         bfin_write_EVT14(evt_default);
 113         bfin_write_EVT15(evt_default);
 114         bfin_write_ILAT(0);
 115         CSYNC();
 116         /* enable hardware error irq */
 117         irq_flags = 0x3f;
 118         local_irq_enable();
 119         return 0;
 120 }