5 #ifndef __BFIN_PERIPHERAL_SDH__
6 #define __BFIN_PERIPHERAL_SDH__
8 /* Bit masks for SDH_COMMAND */
9 #define CMD_IDX 0x3f /* Command Index */
10 #define CMD_RSP 0x40 /* Response */
11 #define CMD_L_RSP 0x80 /* Long Response */
12 #define CMD_INT_E 0x100 /* Command Interrupt */
13 #define CMD_PEND_E 0x200 /* Command Pending */
14 #define CMD_E 0x400 /* Command Enable */
16 #define CMD_CRC_CHECK_D 0x800 /* CRC Check is disabled */
17 #define CMD_DATA0_BUSY 0x1000 /* Check Busy State on DATA0 */
20 /* Bit masks for SDH_PWR_CTL */
22 #define PWR_ON 0x3 /* Power On */
23 #define SD_CMD_OD 0x40 /* Open Drain Output */
24 #define ROD_CTL 0x80 /* Rod Control */
27 /* Bit masks for SDH_CLK_CTL */
28 #define CLKDIV 0xff /* MC_CLK Divisor */
29 #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
30 #define PWR_SV_E 0x200 /* Power Save Enable */
31 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
32 #define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
33 #define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
34 #define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
35 #define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
37 #define CARD_TYPE_MASK 0xe000 /* Card type mask */
38 #define CARD_TYPE_OFFSET 13 /* Card type offset */
39 #define CARD_TYPE_SDIO 0
40 #define CARD_TYPE_eMMC 1
41 #define CARD_TYPE_SD 2
42 #define CARD_TYPE_CEATA 3
45 /* Bit masks for SDH_RESP_CMD */
46 #define RESP_CMD 0x3f /* Response Command */
48 /* Bit masks for SDH_DATA_CTL */
49 #define DTX_E 0x1 /* Data Transfer Enable */
50 #define DTX_DIR 0x2 /* Data Transfer Direction */
51 #define DTX_MODE 0x4 /* Data Transfer Mode */
52 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
54 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
57 /* Bit masks for SDH_BLK_SIZE */
58 #define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
61 /* Bit masks for SDH_STATUS */
62 #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
63 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
64 #define CMD_TIME_OUT 0x4 /* CMD Time Out */
65 #define DAT_TIME_OUT 0x8 /* Data Time Out */
66 #define TX_UNDERRUN 0x10 /* Transmit Underrun */
67 #define RX_OVERRUN 0x20 /* Receive Overrun */
68 #define CMD_RESP_END 0x40 /* CMD Response End */
69 #define CMD_SENT 0x80 /* CMD Sent */
70 #define DAT_END 0x100 /* Data End */
71 #define START_BIT_ERR 0x200 /* Start Bit Error */
72 #define DAT_BLK_END 0x400 /* Data Block End */
73 #define CMD_ACT 0x800 /* CMD Active */
74 #define TX_ACT 0x1000 /* Transmit Active */
75 #define RX_ACT 0x2000 /* Receive Active */
76 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
77 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
78 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
79 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
80 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
81 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
82 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */
83 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */
85 /* Bit masks for SDH_STATUS_CLR */
86 #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
87 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
88 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
89 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
90 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
91 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
92 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
93 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */
94 #define DAT_END_STAT 0x100 /* Data End Status */
95 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
96 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
98 /* Bit masks for SDH_MASK0 */
99 #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
100 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
101 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
102 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
103 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
104 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
105 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
106 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
107 #define DAT_END_MASK 0x100 /* Data End Mask */
108 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
109 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
110 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */
111 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
112 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */
113 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
114 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
115 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
116 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
117 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
118 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
119 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
120 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
122 /* Bit masks for SDH_FIFO_CNT */
123 #define FIFO_COUNT 0x7fff /* FIFO Count */
125 /* Bit masks for SDH_E_STATUS */
126 #define SDIO_INT_DET 0x2 /* SDIO Int Detected */
127 #define SD_CARD_DET 0x10 /* SD Card Detect */
128 #define SD_CARD_BUSYMODE 0x80000000 /* Card is in Busy mode */
129 #define SD_CARD_SLPMODE 0x40000000 /* Card in Sleep Mode */
130 #define SD_CARD_READY 0x00020000 /* Card Ready */
132 /* Bit masks for SDH_E_MASK */
133 #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
134 #define SCD_MSK 0x10 /* Mask Card Detect */
136 /* Bit masks for SDH_CFG */
137 #define CLKS_EN 0x1 /* Clocks Enable */
138 #define SD4E 0x4 /* SDIO 4-Bit Enable */
139 #define MWE 0x8 /* Moving Window Enable */
140 #define SD_RST 0x10 /* SDMMC Reset */
141 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
142 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
144 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
146 #define PWR_ON 0x600 /* Power On */
147 #define SD_CMD_OD 0x800 /* Open Drain Output */
148 #define BOOT_EN 0x1000 /* Boot Enable */
149 #define BOOT_MODE 0x2000 /* Alternate Boot Mode */
150 #define BOOT_ACK_EN 0x4000 /* Boot ACK is expected */
153 /* Bit masks for SDH_RD_WAIT_EN */
154 #define RWR 0x1 /* Read Wait Request */