arch/blackfin/lib/clocks.c

   1 /*
   2  * clocks.c - figure out sclk/cclk/vco and such
   3  *
   4  * Copyright (c) 2005-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/clock.h>
  11
  12 /* Get the voltage input multiplier */
  13 u_long get_vco(void)
  14 {
  15         static u_long cached_vco_pll_ctl, cached_vco;
  16
  17         u_long msel, pll_ctl;
  18
  19         pll_ctl = bfin_read_PLL_CTL();
  20         if (pll_ctl == cached_vco_pll_ctl)
  21                 return cached_vco;
  22         else
  23                 cached_vco_pll_ctl = pll_ctl;
  24
  25         msel = (pll_ctl & MSEL) >> MSEL_P;
  26         if (0 == msel)
  27                 msel = (MSEL >> MSEL_P) + 1;
  28
  29         cached_vco = CONFIG_CLKIN_HZ;
  30         cached_vco >>= (pll_ctl & DF);
  31         cached_vco *= msel;
  32         return cached_vco;
  33 }
  34
  35 /* Get the Core clock */
  36 u_long get_cclk(void)
  37 {
  38         static u_long cached_cclk_pll_div, cached_cclk;
  39         u_long div, csel;
  40 #ifndef CGU_DIV
  41         u_long ssel;
  42 #endif
  43
  44         if (pll_is_bypassed())
  45                 return CONFIG_CLKIN_HZ;
  46
  47         div = bfin_read_PLL_DIV();
  48         if (div == cached_cclk_pll_div)
  49                 return cached_cclk;
  50         else
  51                 cached_cclk_pll_div = div;
  52
  53         csel = (div & CSEL) >> CSEL_P;
  54 #ifndef CGU_DIV
  55         ssel = (div & SSEL) >> SSEL_P;
  56         if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
  57                 cached_cclk = get_vco() / ssel;
  58         else
  59                 cached_cclk = get_vco() >> csel;
  60 #else
  61         cached_cclk = get_vco() / csel;
  62 #endif
  63         return cached_cclk;
  64 }
  65
  66 /* Get the System clock */
  67 #ifdef CGU_DIV
  68
  69 static u_long cached_sclk_pll_div, cached_sclk;
  70 static u_long cached_sclk0, cached_sclk1, cached_dclk;
  71 static u_long _get_sclk(u_long *cache)
  72 {
  73         u_long div, ssel;
  74
  75         if (pll_is_bypassed())
  76                 return CONFIG_CLKIN_HZ;
  77
  78         div = bfin_read_PLL_DIV();
  79         if (div == cached_sclk_pll_div)
  80                 return *cache;
  81         else
  82                 cached_sclk_pll_div = div;
  83
  84         ssel = (div & SYSSEL) >> SYSSEL_P;
  85         cached_sclk = get_vco() / ssel;
  86
  87         ssel = (div & S0SEL) >> S0SEL_P;
  88         cached_sclk0 = cached_sclk / ssel;
  89
  90         ssel = (div & S1SEL) >> S1SEL_P;
  91         cached_sclk1 = cached_sclk / ssel;
  92
  93         ssel = (div & DSEL) >> DSEL_P;
  94         cached_dclk = get_vco() / ssel;
  95
  96         return *cache;
  97 }
  98
  99 u_long get_sclk(void)
 100 {
 101         return _get_sclk(&cached_sclk);
 102 }
 103
 104 u_long get_sclk0(void)
 105 {
 106         return _get_sclk(&cached_sclk0);
 107 }
 108
 109 u_long get_sclk1(void)
 110 {
 111         return _get_sclk(&cached_sclk1);
 112 }
 113
 114 u_long get_dclk(void)
 115 {
 116         return _get_sclk(&cached_dclk);
 117 }
 118 #else
 119
 120 u_long get_sclk(void)
 121 {
 122         static u_long cached_sclk_pll_div, cached_sclk;
 123         u_long div, ssel;
 124
 125         if (pll_is_bypassed())
 126                 return CONFIG_CLKIN_HZ;
 127
 128         div = bfin_read_PLL_DIV();
 129         if (div == cached_sclk_pll_div)
 130                 return cached_sclk;
 131         else
 132                 cached_sclk_pll_div = div;
 133
 134         ssel = (div & SSEL) >> SSEL_P;
 135         cached_sclk = get_vco() / ssel;
 136
 137         return cached_sclk;
 138 }
 139
 140 #endif