arch/powerpc/cpu/mpc83xx/cpu_init.c

   1 /*
   2  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <mpc83xx.h>
  25 #include <ioports.h>
  26 #include <asm/io.h>
  27 #ifdef CONFIG_USB_EHCI_FSL
  28 #include <usb/ehci-fsl.h>
  29 #endif
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #ifdef CONFIG_QE
  34 extern qe_iop_conf_t qe_iop_conf_tab[];
  35 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  36                          int open_drain, int assign);
  37 extern void qe_init(uint qe_base);
  38 extern void qe_reset(void);
  39
  40 static void config_qe_ioports(void)
  41 {
  42         u8      port, pin;
  43         int     dir, open_drain, assign;
  44         int     i;
  45
  46         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  47                 port            = qe_iop_conf_tab[i].port;
  48                 pin             = qe_iop_conf_tab[i].pin;
  49                 dir             = qe_iop_conf_tab[i].dir;
  50                 open_drain      = qe_iop_conf_tab[i].open_drain;
  51                 assign          = qe_iop_conf_tab[i].assign;
  52                 qe_config_iopin(port, pin, dir, open_drain, assign);
  53         }
  54 }
  55 #endif
  56
  57 /*
  58  * Breathe some life into the CPU...
  59  *
  60  * Set up the memory map,
  61  * initialize a bunch of registers,
  62  * initialize the UPM's
  63  */
  64 void cpu_init_f (volatile immap_t * im)
  65 {
  66         __be32 acr_mask =
  67 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  68                 ACR_PIPE_DEP |
  69 #endif
  70 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  71                 ACR_RPTCNT |
  72 #endif
  73 #ifdef CONFIG_SYS_ACR_APARK     /* Arbiter address parking mode */
  74                 ACR_APARK |
  75 #endif
  76 #ifdef CONFIG_SYS_ACR_PARKM     /* Arbiter parking master */
  77                 ACR_PARKM |
  78 #endif
  79                 0;
  80         __be32 acr_val =
  81 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  82                 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
  83 #endif
  84 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  85                 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
  86 #endif
  87 #ifdef CONFIG_SYS_ACR_APARK     /* Arbiter address parking mode */
  88                 (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
  89 #endif
  90 #ifdef CONFIG_SYS_ACR_PARKM     /* Arbiter parking master */
  91                 (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
  92 #endif
  93                 0;
  94         __be32 spcr_mask =
  95 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
  96                 SPCR_OPT |
  97 #endif
  98 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
  99                 SPCR_TSECEP |
 100 #endif
 101 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
 102                 SPCR_TSEC1EP |
 103 #endif
 104 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
 105                 SPCR_TSEC2EP |
 106 #endif
 107                 0;
 108         __be32 spcr_val =
 109 #ifdef CONFIG_SYS_SPCR_OPT
 110                 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
 111 #endif
 112 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
 113                 (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
 114 #endif
 115 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
 116                 (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
 117 #endif
 118 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
 119                 (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
 120 #endif
 121                 0;
 122         __be32 sccr_mask =
 123 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 124                 SCCR_ENCCM |
 125 #endif
 126 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 127                 SCCR_PCICM |
 128 #endif
 129 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 130                 SCCR_TSECCM |
 131 #endif
 132 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 133                 SCCR_TSEC1CM |
 134 #endif
 135 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 136                 SCCR_TSEC2CM |
 137 #endif
 138 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 139                 SCCR_TSEC1ON |
 140 #endif
 141 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 142                 SCCR_TSEC2ON |
 143 #endif
 144 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 145                 SCCR_USBMPHCM |
 146 #endif
 147 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 148                 SCCR_USBDRCM |
 149 #endif
 150 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 151                 SCCR_SATACM |
 152 #endif
 153                 0;
 154         __be32 sccr_val =
 155 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 156                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 157 #endif
 158 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 159                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 160 #endif
 161 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 162                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 163 #endif
 164 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 165                 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 166 #endif
 167 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 168                 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 169 #endif
 170 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 171                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 172 #endif
 173 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 174                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 175 #endif
 176 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 177                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 178 #endif
 179 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 180                 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 181 #endif
 182 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 183                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 184 #endif
 185                 0;
 186         __be32 lcrr_mask =
 187 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 188                 LCRR_DBYP |
 189 #endif
 190 #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
 191                 LCRR_EADC |
 192 #endif
 193 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 194                 LCRR_CLKDIV |
 195 #endif
 196                 0;
 197         __be32 lcrr_val =
 198 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 199                 CONFIG_SYS_LCRR_DBYP |
 200 #endif
 201 #ifdef CONFIG_SYS_LCRR_EADC
 202                 CONFIG_SYS_LCRR_EADC |
 203 #endif
 204 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 205                 CONFIG_SYS_LCRR_CLKDIV |
 206 #endif
 207                 0;
 208
 209         /* Pointer is writable since we allocated a register for it */
 210         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 211
 212         /* Clear initial global data */
 213         memset ((void *) gd, 0, sizeof (gd_t));
 214
 215         /* system performance tweaking */
 216         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 217
 218         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 219
 220         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 221
 222         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 223         gd->reset_status = __raw_readl(&im->reset.rsr);
 224         __raw_writel(~(RSR_RES), &im->reset.rsr);
 225
 226         /* AER - Arbiter Event Register - store status */
 227         gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 228         gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 229
 230         /*
 231          * RMR - Reset Mode Register
 232          * contains checkstop reset enable (4.6.1.4)
 233          */
 234         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 235
 236         /* LCRR - Clock Ratio Register (10.3.1.16)
 237          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 238          */
 239         clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
 240         __raw_readl(&im->im_lbc.lcrr);
 241         isync();
 242
 243         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 244         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 245
 246         /* System General Purpose Register */
 247 #ifdef CONFIG_SYS_SICRH
 248 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
 249         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 250         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 251                      &im->sysconf.sicrh);
 252 #else
 253         __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 254 #endif
 255 #endif
 256 #ifdef CONFIG_SYS_SICRL
 257         __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 258 #endif
 259 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 260         __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 261 #endif
 262 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
 263         __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 264 #endif
 265
 266 #ifdef CONFIG_QE
 267         /* Config QE ioports */
 268         config_qe_ioports();
 269 #endif
 270         /* Set up preliminary BR/OR regs */
 271         init_early_memctl_regs();
 272
 273         /* Local Access window setup */
 274 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 275         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 276         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 277 #else
 278 #error  CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 279 #endif
 280
 281 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 282         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 283         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 284 #endif
 285 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 286         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 287         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 288 #endif
 289 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 290         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 291         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 292 #endif
 293 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 294         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 295         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 296 #endif
 297 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 298         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 299         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 300 #endif
 301 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 302         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 303         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 304 #endif
 305 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 306         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 307         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 308 #endif
 309 #ifdef CONFIG_SYS_GPIO1_PRELIM
 310         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 311         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 312 #endif
 313 #ifdef CONFIG_SYS_GPIO2_PRELIM
 314         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 315         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 316 #endif
 317 #ifdef CONFIG_USB_EHCI_FSL
 318 #ifndef CONFIG_MPC834x
 319         uint32_t temp;
 320         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
 321
 322         /* Configure interface. */
 323         setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 324
 325         /* Wait for clock to stabilize */
 326         do {
 327                 temp = __raw_readl(&ehci->control);
 328                 udelay(1000);
 329         } while (!(temp & PHY_CLK_VALID));
 330 #endif
 331 #endif
 332 }
 333
 334 int cpu_init_r (void)
 335 {
 336 #ifdef CONFIG_QE
 337         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 338
 339         qe_init(qe_base);
 340         qe_reset();
 341 #endif
 342         return 0;
 343 }
 344
 345 /*
 346  * Print out the bus arbiter event
 347  */
 348 #if defined(CONFIG_DISPLAY_AER_FULL)
 349 static int print_83xx_arb_event(int force)
 350 {
 351         static char* event[] = {
 352                 "Address Time Out",
 353                 "Data Time Out",
 354                 "Address Only Transfer Type",
 355                 "External Control Word Transfer Type",
 356                 "Reserved Transfer Type",
 357                 "Transfer Error",
 358                 "reserved",
 359                 "reserved"
 360         };
 361         static char* master[] = {
 362                 "e300 Core Data Transaction",
 363                 "reserved",
 364                 "e300 Core Instruction Fetch",
 365                 "reserved",
 366                 "TSEC1",
 367                 "TSEC2",
 368                 "USB MPH",
 369                 "USB DR",
 370                 "Encryption Core",
 371                 "I2C Boot Sequencer",
 372                 "JTAG",
 373                 "reserved",
 374                 "eSDHC",
 375                 "PCI1",
 376                 "PCI2",
 377                 "DMA",
 378                 "QUICC Engine 00",
 379                 "QUICC Engine 01",
 380                 "QUICC Engine 10",
 381                 "QUICC Engine 11",
 382                 "reserved",
 383                 "reserved",
 384                 "reserved",
 385                 "reserved",
 386                 "SATA1",
 387                 "SATA2",
 388                 "SATA3",
 389                 "SATA4",
 390                 "reserved",
 391                 "PCI Express 1",
 392                 "PCI Express 2",
 393                 "TDM-DMAC"
 394         };
 395         static char *transfer[] = {
 396                 "Address-only, Clean Block",
 397                 "Address-only, lwarx reservation set",
 398                 "Single-beat or Burst write",
 399                 "reserved",
 400                 "Address-only, Flush Block",
 401                 "reserved",
 402                 "Burst write",
 403                 "reserved",
 404                 "Address-only, sync",
 405                 "Address-only, tlbsync",
 406                 "Single-beat or Burst read",
 407                 "Single-beat or Burst read",
 408                 "Address-only, Kill Block",
 409                 "Address-only, icbi",
 410                 "Burst read",
 411                 "reserved",
 412                 "Address-only, eieio",
 413                 "reserved",
 414                 "Single-beat write",
 415                 "reserved",
 416                 "ecowx - Illegal single-beat write",
 417                 "reserved",
 418                 "reserved",
 419                 "reserved",
 420                 "Address-only, TLB Invalidate",
 421                 "reserved",
 422                 "Single-beat or Burst read",
 423                 "reserved",
 424                 "eciwx - Illegal single-beat read",
 425                 "reserved",
 426                 "Burst read",
 427                 "reserved"
 428         };
 429
 430         int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
 431                     >> AEATR_EVENT_SHIFT;
 432         int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
 433                       >> AEATR_MSTR_ID_SHIFT;
 434         int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
 435                    >> AEATR_TBST_SHIFT;
 436         int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
 437                     >> AEATR_TSIZE_SHIFT;
 438         int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
 439                     >> AEATR_TTYPE_SHIFT;
 440
 441         if (!force && !gd->arbiter_event_address)
 442                 return 0;
 443
 444         puts("Arbiter Event Status:\n");
 445         printf("       Event Address: 0x%08lX\n", gd->arbiter_event_address);
 446         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 447         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 448         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 449                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 450         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 451
 452         return gd->arbiter_event_address;
 453 }
 454
 455 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 456
 457 static int print_83xx_arb_event(int force)
 458 {
 459         if (!force && !gd->arbiter_event_address)
 460                 return 0;
 461
 462         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 463                 gd->arbiter_event_attributes, gd->arbiter_event_address);
 464
 465         return gd->arbiter_event_address;
 466 }
 467 #endif /* CONFIG_DISPLAY_AER_xxxx */
 468
 469 /*
 470  * Figure out the cause of the reset
 471  */
 472 int prt_83xx_rsr(void)
 473 {
 474         static struct {
 475                 ulong mask;
 476                 char *desc;
 477         } bits[] = {
 478                 {
 479                 RSR_SWSR, "Software Soft"}, {
 480                 RSR_SWHR, "Software Hard"}, {
 481                 RSR_JSRS, "JTAG Soft"}, {
 482                 RSR_CSHR, "Check Stop"}, {
 483                 RSR_SWRS, "Software Watchdog"}, {
 484                 RSR_BMRS, "Bus Monitor"}, {
 485                 RSR_SRS,  "External/Internal Soft"}, {
 486                 RSR_HRS,  "External/Internal Hard"}
 487         };
 488         static int n = sizeof bits / sizeof bits[0];
 489         ulong rsr = gd->reset_status;
 490         int i;
 491         char *sep;
 492
 493         puts("Reset Status:");
 494
 495         sep = " ";
 496         for (i = 0; i < n; i++)
 497                 if (rsr & bits[i].mask) {
 498                         printf("%s%s", sep, bits[i].desc);
 499                         sep = ", ";
 500                 }
 501         puts("\n");
 502
 503 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 504         print_83xx_arb_event(rsr & RSR_BMRS);
 505 #endif
 506         puts("\n");
 507
 508         return 0;
 509 }