2 * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <fsl_esdhc.h>
33 #include <asm/cache.h>
36 DECLARE_GLOBAL_DATA_PTR;
46 char buf1[32], buf2[32];
47 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48 #ifdef CONFIG_DDR_CLK_FREQ
49 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
50 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
52 #ifdef CONFIG_FSL_CORENET
53 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
54 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
57 #endif /* CONFIG_FSL_CORENET */
58 #endif /* CONFIG_DDR_CLK_FREQ */
64 major &= 0x7; /* the msb of this nibble is a mfg code */
68 if (cpu_numcores() > 1) {
70 puts("Unicore software on multiprocessor system!!\n"
71 "To enable mutlticore build define CONFIG_MP\n");
73 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
74 printf("CPU%d: ", pic->whoami);
82 if (IS_E_PROCESSOR(svr))
85 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
95 case PVR_FAM(PVR_85xx):
103 if (PVR_MEM(pvr) == 0x03)
106 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
108 get_sys_info(&sysinfo);
110 puts("Clock Configuration:");
111 for (i = 0; i < cpu_numcores(); i++) {
114 printf("CPU%d:%-4s MHz, ",
115 i,strmhz(buf1, sysinfo.freqProcessor[i]));
117 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
119 #ifdef CONFIG_FSL_CORENET
121 printf(" DDR:%-4s MHz (%s MT/s data rate) "
123 strmhz(buf1, sysinfo.freqDDRBus/2),
124 strmhz(buf2, sysinfo.freqDDRBus));
126 printf(" DDR:%-4s MHz (%s MT/s data rate) "
128 strmhz(buf1, sysinfo.freqDDRBus/2),
129 strmhz(buf2, sysinfo.freqDDRBus));
134 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
135 strmhz(buf1, sysinfo.freqDDRBus/2),
136 strmhz(buf2, sysinfo.freqDDRBus));
139 printf(" DDR:%-4s MHz (%s MT/s data rate) "
141 strmhz(buf1, sysinfo.freqDDRBus/2),
142 strmhz(buf2, sysinfo.freqDDRBus));
145 printf(" DDR:%-4s MHz (%s MT/s data rate) "
147 strmhz(buf1, sysinfo.freqDDRBus/2),
148 strmhz(buf2, sysinfo.freqDDRBus));
153 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
154 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
156 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
157 sysinfo.freqLocalBus);
161 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
165 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
168 #ifdef CONFIG_SYS_DPAA_FMAN
169 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
170 printf(" FMAN%d: %s MHz\n", i,
171 strmhz(buf1, sysinfo.freqFMan[i]));
175 #ifdef CONFIG_SYS_DPAA_PME
176 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
179 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
185 /* ------------------------------------------------------------------------- */
187 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
189 /* Everything after the first generation of PQ3 parts has RSTCR */
190 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
191 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
192 unsigned long val, msr;
195 * Initiate hard reset in debug control register DBCR0
196 * Make sure MSR[DE] = 1. This only resets the core.
206 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
207 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
216 * Get timebase clock frequency
218 unsigned long get_tbclk (void)
220 #ifdef CONFIG_FSL_CORENET
221 return (gd->bus_clk + 8) / 16;
223 return (gd->bus_clk + 4UL)/8UL;
228 #if defined(CONFIG_WATCHDOG)
232 int re_enable = disable_interrupts();
233 reset_85xx_watchdog();
234 if (re_enable) enable_interrupts();
238 reset_85xx_watchdog(void)
241 * Clear TSR(WIS) bit by writing 1
244 val = mfspr(SPRN_TSR);
246 mtspr(SPRN_TSR, val);
248 #endif /* CONFIG_WATCHDOG */
251 * Configures a UPM. The function requires the respective MxMR to be set
252 * before calling this function. "size" is the number or entries, not a sizeof.
254 void upmconfig (uint upm, uint * table, uint size)
256 int i, mdr, mad, old_mad = 0;
258 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
259 volatile u32 *brp,*orp;
260 volatile u8* dummy = NULL;
266 upmmask = BR_MS_UPMA;
270 upmmask = BR_MS_UPMB;
274 upmmask = BR_MS_UPMC;
277 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
281 /* Find the address for the dummy write transaction */
282 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
283 i++, brp += 2, orp += 2) {
285 /* Look for a valid BR with selected UPM */
286 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
287 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
293 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
297 for (i = 0; i < size; i++) {
299 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
301 out_be32(&lbc->mdr, table[i]);
303 mdr = in_be32(&lbc->mdr);
305 *(volatile u8 *)dummy = 0;
308 mad = in_be32(mxmr) & MxMR_MAD_MSK;
309 } while (mad <= old_mad && !(!mad && i == (size-1)));
312 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
316 * Initializes on-chip MMC controllers.
317 * to override, implement board_mmc_init()
319 int cpu_mmc_init(bd_t *bis)
321 #ifdef CONFIG_FSL_ESDHC
322 return fsl_esdhc_mmc_init(bis);