arch/powerpc/cpu/mpc85xx/cpu_init.c

   1 /*
   2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2003 Motorola Inc.
   5  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   6  *
   7  * (C) Copyright 2000
   8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <watchdog.h>
  15 #include <asm/processor.h>
  16 #include <ioports.h>
  17 #include <sata.h>
  18 #include <fm_eth.h>
  19 #include <asm/io.h>
  20 #include <asm/cache.h>
  21 #include <asm/mmu.h>
  22 #include <asm/fsl_errata.h>
  23 #include <asm/fsl_law.h>
  24 #include <asm/fsl_serdes.h>
  25 #include <asm/fsl_srio.h>
  26 #include <fsl_usb.h>
  27 #include <hwconfig.h>
  28 #include <linux/compiler.h>
  29 #include "mp.h"
  30 #ifdef CONFIG_FSL_CAAM
  31 #include <fsl_sec.h>
  32 #endif
  33 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
  34 #include <nand.h>
  35 #include <errno.h>
  36 #endif
  37
  38 #include "../../../../drivers/block/fsl_sata.h"
  39 #ifdef CONFIG_U_QE
  40 #include "../../../../drivers/qe/qe.h"
  41 #endif
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  46 /*
  47  * For deriving usb clock from 100MHz sysclk, reference divisor is set
  48  * to a value of 5, which gives an intermediate value 20(100/5). The
  49  * multiplication factor integer is set to 24, which when multiplied to
  50  * above intermediate value provides clock for usb ip.
  51  */
  52 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
  53 {
  54         sys_info_t sysinfo;
  55
  56         get_sys_info(&sysinfo);
  57         if (sysinfo.diff_sysclk == 1) {
  58                 clrbits_be32(&usb_phy->pllprg[1],
  59                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
  60                 setbits_be32(&usb_phy->pllprg[1],
  61                              CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
  62                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
  63                              CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
  64                 }
  65 }
  66 #endif
  67
  68 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  69 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
  70 {
  71 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  72         u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
  73
  74         /* Increase Disconnect Threshold by 50mV */
  75         xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  76                                                 INC_DCNT_THRESHOLD_50MV;
  77         /* Enable programming of USB High speed Disconnect threshold */
  78         xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  79         out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
  80
  81         xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
  82         /* Increase Disconnect Threshold by 50mV */
  83         xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  84                                                 INC_DCNT_THRESHOLD_50MV;
  85         /* Enable programming of USB High speed Disconnect threshold */
  86         xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  87         out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
  88 #else
  89
  90         u32 temp = 0;
  91         u32 status = in_be32(&usb_phy->status1);
  92
  93         u32 squelch_prog_rd_0_2 =
  94                 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
  95                         & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  96
  97         u32 squelch_prog_rd_3_5 =
  98                 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
  99                         & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
 100
 101         setbits_be32(&usb_phy->config1,
 102                      CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
 103         setbits_be32(&usb_phy->config2,
 104                      CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
 105
 106         temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
 107         out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
 108
 109         temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
 110         out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
 111 #endif
 112 }
 113 #endif
 114
 115
 116 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
 117 extern qe_iop_conf_t qe_iop_conf_tab[];
 118 extern void qe_config_iopin(u8 port, u8 pin, int dir,
 119                                 int open_drain, int assign);
 120 extern void qe_init(uint qe_base);
 121 extern void qe_reset(void);
 122
 123 static void config_qe_ioports(void)
 124 {
 125         u8      port, pin;
 126         int     dir, open_drain, assign;
 127         int     i;
 128
 129         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
 130                 port            = qe_iop_conf_tab[i].port;
 131                 pin             = qe_iop_conf_tab[i].pin;
 132                 dir             = qe_iop_conf_tab[i].dir;
 133                 open_drain      = qe_iop_conf_tab[i].open_drain;
 134                 assign          = qe_iop_conf_tab[i].assign;
 135                 qe_config_iopin(port, pin, dir, open_drain, assign);
 136         }
 137 }
 138 #endif
 139
 140 #ifdef CONFIG_CPM2
 141 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 142 {
 143         int portnum;
 144
 145         for (portnum = 0; portnum < 4; portnum++) {
 146                 uint pmsk = 0,
 147                      ppar = 0,
 148                      psor = 0,
 149                      pdir = 0,
 150                      podr = 0,
 151                      pdat = 0;
 152                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
 153                 iop_conf_t *eiopc = iopc + 32;
 154                 uint msk = 1;
 155
 156                 /*
 157                  * NOTE:
 158                  * index 0 refers to pin 31,
 159                  * index 31 refers to pin 0
 160                  */
 161                 while (iopc < eiopc) {
 162                         if (iopc->conf) {
 163                                 pmsk |= msk;
 164                                 if (iopc->ppar)
 165                                         ppar |= msk;
 166                                 if (iopc->psor)
 167                                         psor |= msk;
 168                                 if (iopc->pdir)
 169                                         pdir |= msk;
 170                                 if (iopc->podr)
 171                                         podr |= msk;
 172                                 if (iopc->pdat)
 173                                         pdat |= msk;
 174                         }
 175
 176                         msk <<= 1;
 177                         iopc++;
 178                 }
 179
 180                 if (pmsk != 0) {
 181                         volatile ioport_t *iop = ioport_addr (cpm, portnum);
 182                         uint tpmsk = ~pmsk;
 183
 184                         /*
 185                          * the (somewhat confused) paragraph at the
 186                          * bottom of page 35-5 warns that there might
 187                          * be "unknown behaviour" when programming
 188                          * PSORx and PDIRx, if PPARx = 1, so I
 189                          * decided this meant I had to disable the
 190                          * dedicated function first, and enable it
 191                          * last.
 192                          */
 193                         iop->ppar &= tpmsk;
 194                         iop->psor = (iop->psor & tpmsk) | psor;
 195                         iop->podr = (iop->podr & tpmsk) | podr;
 196                         iop->pdat = (iop->pdat & tpmsk) | pdat;
 197                         iop->pdir = (iop->pdir & tpmsk) | pdir;
 198                         iop->ppar |= ppar;
 199                 }
 200         }
 201 }
 202 #endif
 203
 204 #ifdef CONFIG_SYS_FSL_CPC
 205 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
 206 void disable_cpc_sram(void)
 207 {
 208         int i;
 209
 210         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 211
 212         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 213                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
 214                         /* find and disable LAW of SRAM */
 215                         struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
 216
 217                         if (law.index == -1) {
 218                                 printf("\nFatal error happened\n");
 219                                 return;
 220                         }
 221                         disable_law(law.index);
 222
 223                         clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
 224                         out_be32(&cpc->cpccsr0, 0);
 225                         out_be32(&cpc->cpcsrcr0, 0);
 226                 }
 227         }
 228 }
 229 #endif
 230
 231 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
 232 #ifdef CONFIG_POST
 233 #error POST memory test cannot be enabled with TDM
 234 #endif
 235 static void enable_tdm_law(void)
 236 {
 237         int ret;
 238         char buffer[HWCONFIG_BUFFER_SIZE] = {0};
 239         int tdm_hwconfig_enabled = 0;
 240
 241         /*
 242          * Extract hwconfig from environment since environment
 243          * is not setup properly yet. Search for tdm entry in
 244          * hwconfig.
 245          */
 246         ret = getenv_f("hwconfig", buffer, sizeof(buffer));
 247         if (ret > 0) {
 248                 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
 249                 /* If tdm is defined in hwconfig, set law for tdm workaround */
 250                 if (tdm_hwconfig_enabled)
 251                         set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
 252                                      LAW_TRGT_IF_CCSR);
 253         }
 254 }
 255 #endif
 256
 257 void enable_cpc(void)
 258 {
 259         int i;
 260         int ret;
 261         u32 size = 0;
 262         u32 cpccfg0;
 263         char buffer[HWCONFIG_BUFFER_SIZE];
 264         char cpc_subarg[16];
 265         bool have_hwconfig = false;
 266         int cpc_args = 0;
 267         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 268
 269         /* Extract hwconfig from environment */
 270         ret = getenv_f("hwconfig", buffer, sizeof(buffer));
 271         if (ret > 0) {
 272                 /*
 273                  * If "en_cpc" is not defined in hwconfig then by default all
 274                  * cpcs are enable. If this config is defined then individual
 275                  * cpcs which have to be enabled should also be defined.
 276                  * e.g en_cpc:cpc1,cpc2;
 277                  */
 278                 if (hwconfig_f("en_cpc", buffer))
 279                         have_hwconfig = true;
 280         }
 281
 282         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 283                 if (have_hwconfig) {
 284                         sprintf(cpc_subarg, "cpc%u", i + 1);
 285                         cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
 286                         if (cpc_args == 0)
 287                                 continue;
 288                 }
 289                 cpccfg0 = in_be32(&cpc->cpccfg0);
 290                 size += CPC_CFG0_SZ_K(cpccfg0);
 291
 292 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
 293                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
 294 #endif
 295 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
 296                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
 297 #endif
 298 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 299                 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
 300 #endif
 301 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
 302                 if (has_erratum_a006379()) {
 303                         setbits_be32(&cpc->cpchdbcr0,
 304                                      CPC_HDBCR0_SPLRU_LEVEL_EN);
 305                 }
 306 #endif
 307
 308                 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 309                 /* Read back to sync write */
 310                 in_be32(&cpc->cpccsr0);
 311
 312         }
 313
 314         puts("Corenet Platform Cache: ");
 315         print_size(size * 1024, " enabled\n");
 316 }
 317
 318 static void invalidate_cpc(void)
 319 {
 320         int i;
 321         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 322
 323         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 324                 /* skip CPC when it used as all SRAM */
 325                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
 326                         continue;
 327                 /* Flash invalidate the CPC and clear all the locks */
 328                 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
 329                 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
 330                         ;
 331         }
 332 }
 333 #else
 334 #define enable_cpc()
 335 #define invalidate_cpc()
 336 #define disable_cpc_sram()
 337 #endif /* CONFIG_SYS_FSL_CPC */
 338
 339 /*
 340  * Breathe some life into the CPU...
 341  *
 342  * Set up the memory map
 343  * initialize a bunch of registers
 344  */
 345
 346 #ifdef CONFIG_FSL_CORENET
 347 static void corenet_tb_init(void)
 348 {
 349         volatile ccsr_rcpm_t *rcpm =
 350                 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 351         volatile ccsr_pic_t *pic =
 352                 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 353         u32 whoami = in_be32(&pic->whoami);
 354
 355         /* Enable the timebase register for this core */
 356         out_be32(&rcpm->ctbenrl, (1 << whoami));
 357 }
 358 #endif
 359
 360 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 361 void fsl_erratum_a007212_workaround(void)
 362 {
 363         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 364         u32 ddr_pll_ratio;
 365         u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
 366         u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
 367         u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
 368 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 369         u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
 370         u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
 371 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
 372         u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
 373         u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
 374 #endif
 375 #endif
 376         /*
 377          * Even this workaround applies to selected version of SoCs, it is
 378          * safe to apply to all versions, with the limitation of odd ratios.
 379          * If RCW has disabled DDR PLL, we have to apply this workaround,
 380          * otherwise DDR will not work.
 381          */
 382         ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
 383                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
 384                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 385         /* check if RCW sets ratio to 0, required by this workaround */
 386         if (ddr_pll_ratio != 0)
 387                 return;
 388         ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
 389                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
 390                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 391         /* check if reserved bits have the desired ratio */
 392         if (ddr_pll_ratio == 0) {
 393                 printf("Error: Unknown DDR PLL ratio!\n");
 394                 return;
 395         }
 396         ddr_pll_ratio >>= 1;
 397
 398         setbits_be32(plldadcr1, 0x02000001);
 399 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 400         setbits_be32(plldadcr2, 0x02000001);
 401 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
 402         setbits_be32(plldadcr3, 0x02000001);
 403 #endif
 404 #endif
 405         setbits_be32(dpdovrcr4, 0xe0000000);
 406         out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
 407 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 408         out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
 409 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
 410         out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
 411 #endif
 412 #endif
 413         udelay(100);
 414         clrbits_be32(plldadcr1, 0x02000001);
 415 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 416         clrbits_be32(plldadcr2, 0x02000001);
 417 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
 418         clrbits_be32(plldadcr3, 0x02000001);
 419 #endif
 420 #endif
 421         clrbits_be32(dpdovrcr4, 0xe0000000);
 422 }
 423 #endif
 424
 425 ulong cpu_init_f(void)
 426 {
 427         ulong flag = 0;
 428         extern void m8560_cpm_reset (void);
 429 #if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
 430         (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
 431         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 432 #endif
 433 #if defined(CONFIG_SECURE_BOOT)
 434         struct law_entry law;
 435 #endif
 436 #ifdef CONFIG_MPC8548
 437         ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 438         uint svr = get_svr();
 439
 440         /*
 441          * CPU2 errata workaround: A core hang possible while executing
 442          * a msync instruction and a snoopable transaction from an I/O
 443          * master tagged to make quick forward progress is present.
 444          * Fixed in silicon rev 2.1.
 445          */
 446         if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
 447                 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 448 #endif
 449
 450         disable_tlb(14);
 451         disable_tlb(15);
 452
 453 #if defined(CONFIG_SECURE_BOOT)
 454         /* Disable the LAW created for NOR flash by the PBI commands */
 455         law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
 456         if (law.index != -1)
 457                 disable_law(law.index);
 458
 459 #if defined(CONFIG_SYS_CPC_REINIT_F)
 460         disable_cpc_sram();
 461 #endif
 462
 463 #if defined(CONFIG_FSL_CORENET)
 464         /* Put PAMU in bypass mode */
 465         out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
 466 #endif
 467
 468 #endif
 469
 470 #ifdef CONFIG_CPM2
 471         config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 472 #endif
 473
 474        init_early_memctl_regs();
 475
 476 #if defined(CONFIG_CPM2)
 477         m8560_cpm_reset();
 478 #endif
 479
 480 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
 481         /* Config QE ioports */
 482         config_qe_ioports();
 483 #endif
 484
 485 #if defined(CONFIG_FSL_DMA)
 486         dma_init();
 487 #endif
 488 #ifdef CONFIG_FSL_CORENET
 489         corenet_tb_init();
 490 #endif
 491         init_used_tlb_cams();
 492
 493         /* Invalidate the CPC before DDR gets enabled */
 494         invalidate_cpc();
 495
 496  #ifdef CONFIG_SYS_DCSRBAR_PHYS
 497         /* set DCSRCR so that DCSR space is 1G */
 498         setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
 499         in_be32(&gur->dcsrcr);
 500 #endif
 501
 502 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 503 #ifdef CONFIG_DEEP_SLEEP
 504         /* disable the console if boot from deep sleep */
 505         if (in_be32(&gur->scrtsr[0]) & (1 << 3))
 506                 flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
 507 #endif
 508 #endif
 509 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 510         fsl_erratum_a007212_workaround();
 511 #endif
 512
 513         return flag;
 514 }
 515
 516 /* Implement a dummy function for those platforms w/o SERDES */
 517 static void __fsl_serdes__init(void)
 518 {
 519         return ;
 520 }
 521 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 522
 523 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 524 int enable_cluster_l2(void)
 525 {
 526         int i = 0;
 527         u32 cluster, svr = get_svr();
 528         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 529         struct ccsr_cluster_l2 __iomem *l2cache;
 530
 531         /* only the L2 of first cluster should be enabled as expected on T4080,
 532          * but there is no EOC in the first cluster as HW sake, so return here
 533          * to skip enabling L2 cache of the 2nd cluster.
 534          */
 535         if (SVR_SOC_VER(svr) == SVR_T4080)
 536                 return 0;
 537
 538         cluster = in_be32(&gur->tp_cluster[i].lower);
 539         if (cluster & TP_CLUSTER_EOC)
 540                 return 0;
 541
 542         /* The first cache has already been set up, so skip it */
 543         i++;
 544
 545         /* Look through the remaining clusters, and set up their caches */
 546         do {
 547                 int j, cluster_valid = 0;
 548
 549                 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
 550
 551                 cluster = in_be32(&gur->tp_cluster[i].lower);
 552
 553                 /* check that at least one core/accel is enabled in cluster */
 554                 for (j = 0; j < 4; j++) {
 555                         u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
 556                         u32 type = in_be32(&gur->tp_ityp[idx]);
 557
 558                         if ((type & TP_ITYP_AV) &&
 559                             TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
 560                                 cluster_valid = 1;
 561                 }
 562
 563                 if (cluster_valid) {
 564                         /* set stash ID to (cluster) * 2 + 32 + 1 */
 565                         clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
 566
 567                         printf("enable l2 for cluster %d %p\n", i, l2cache);
 568
 569                         out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
 570                         while ((in_be32(&l2cache->l2csr0)
 571                                 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
 572                                         ;
 573                         out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
 574                 }
 575                 i++;
 576         } while (!(cluster & TP_CLUSTER_EOC));
 577
 578         return 0;
 579 }
 580 #endif
 581
 582 /*
 583  * Initialize L2 as cache.
 584  */
 585 int l2cache_init(void)
 586 {
 587         __maybe_unused u32 svr = get_svr();
 588 #ifdef CONFIG_L2_CACHE
 589         ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
 590 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 591         struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 592 #endif
 593
 594         puts ("L2:    ");
 595
 596 #if defined(CONFIG_L2_CACHE)
 597         volatile uint cache_ctl;
 598         uint ver;
 599         u32 l2siz_field;
 600
 601         ver = SVR_SOC_VER(svr);
 602
 603         asm("msync;isync");
 604         cache_ctl = l2cache->l2ctl;
 605
 606 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 607         if (cache_ctl & MPC85xx_L2CTL_L2E) {
 608                 /* Clear L2 SRAM memory-mapped base address */
 609                 out_be32(&l2cache->l2srbar0, 0x0);
 610                 out_be32(&l2cache->l2srbar1, 0x0);
 611
 612                 /* set MBECCDIS=0, SBECCDIS=0 */
 613                 clrbits_be32(&l2cache->l2errdis,
 614                                 (MPC85xx_L2ERRDIS_MBECC |
 615                                  MPC85xx_L2ERRDIS_SBECC));
 616
 617                 /* set L2E=0, L2SRAM=0 */
 618                 clrbits_be32(&l2cache->l2ctl,
 619                                 (MPC85xx_L2CTL_L2E |
 620                                  MPC85xx_L2CTL_L2SRAM_ENTIRE));
 621         }
 622 #endif
 623
 624         l2siz_field = (cache_ctl >> 28) & 0x3;
 625
 626         switch (l2siz_field) {
 627         case 0x0:
 628                 printf(" unknown size (0x%08x)\n", cache_ctl);
 629                 return -1;
 630                 break;
 631         case 0x1:
 632                 if (ver == SVR_8540 || ver == SVR_8560   ||
 633                     ver == SVR_8541 || ver == SVR_8555) {
 634                         puts("128 KiB ");
 635                         /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
 636                         cache_ctl = 0xc4000000;
 637                 } else {
 638                         puts("256 KiB ");
 639                         cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 640                 }
 641                 break;
 642         case 0x2:
 643                 if (ver == SVR_8540 || ver == SVR_8560   ||
 644                     ver == SVR_8541 || ver == SVR_8555) {
 645                         puts("256 KiB ");
 646                         /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
 647                         cache_ctl = 0xc8000000;
 648                 } else {
 649                         puts("512 KiB ");
 650                         /* set L2E=1, L2I=1, & L2SRAM=0 */
 651                         cache_ctl = 0xc0000000;
 652                 }
 653                 break;
 654         case 0x3:
 655                 puts("1024 KiB ");
 656                 /* set L2E=1, L2I=1, & L2SRAM=0 */
 657                 cache_ctl = 0xc0000000;
 658                 break;
 659         }
 660
 661         if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 662                 puts("already enabled");
 663 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
 664                 u32 l2srbar = l2cache->l2srbar0;
 665                 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 666                                 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
 667                         l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 668                         l2cache->l2srbar0 = l2srbar;
 669                         printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 670                 }
 671 #endif /* CONFIG_SYS_INIT_L2_ADDR */
 672                 puts("\n");
 673         } else {
 674                 asm("msync;isync");
 675                 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 676                 asm("msync;isync");
 677                 puts("enabled\n");
 678         }
 679 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 680         if (SVR_SOC_VER(svr) == SVR_P2040) {
 681                 puts("N/A\n");
 682                 goto skip_l2;
 683         }
 684
 685         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 686
 687         /* invalidate the L2 cache */
 688         mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
 689         while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
 690                 ;
 691
 692 #ifdef CONFIG_SYS_CACHE_STASHING
 693         /* set stash id to (coreID) * 2 + 32 + L2 (1) */
 694         mtspr(SPRN_L2CSR1, (32 + 1));
 695 #endif
 696
 697         /* enable the cache */
 698         mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 699
 700         if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
 701                 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
 702                         ;
 703                 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
 704         }
 705
 706 skip_l2:
 707 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 708         if (l2cache->l2csr0 & L2CSR0_L2E)
 709                 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
 710                            " enabled\n");
 711
 712         enable_cluster_l2();
 713 #else
 714         puts("disabled\n");
 715 #endif
 716
 717         return 0;
 718 }
 719
 720 /*
 721  *
 722  * The newer 8548, etc, parts have twice as much cache, but
 723  * use the same bit-encoding as the older 8555, etc, parts.
 724  *
 725  */
 726 int cpu_init_r(void)
 727 {
 728         __maybe_unused u32 svr = get_svr();
 729 #ifdef CONFIG_SYS_LBC_LCRR
 730         fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
 731 #endif
 732 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
 733         extern int spin_table_compat;
 734         const char *spin;
 735 #endif
 736 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 737         ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
 738 #endif
 739 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 740         defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 741         /*
 742          * CPU22 and NMG_CPU_A011 share the same workaround.
 743          * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 744          * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 745          * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
 746          * fixed in 2.0. NMG_CPU_A011 is activated by default and can
 747          * be disabled by hwconfig with syntax:
 748          *
 749          * fsl_cpu_a011:disable
 750          */
 751         extern int enable_cpu_a011_workaround;
 752 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
 753         enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
 754 #else
 755         char buffer[HWCONFIG_BUFFER_SIZE];
 756         char *buf = NULL;
 757         int n, res;
 758
 759         n = getenv_f("hwconfig", buffer, sizeof(buffer));
 760         if (n > 0)
 761                 buf = buffer;
 762
 763         res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
 764         if (res > 0) {
 765                 enable_cpu_a011_workaround = 0;
 766         } else {
 767                 if (n >= HWCONFIG_BUFFER_SIZE) {
 768                         printf("fsl_cpu_a011 was not found. hwconfig variable "
 769                                 "may be too long\n");
 770                 }
 771                 enable_cpu_a011_workaround =
 772                         (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
 773                         (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
 774         }
 775 #endif
 776         if (enable_cpu_a011_workaround) {
 777                 flush_dcache();
 778                 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
 779                 sync();
 780         }
 781 #endif
 782 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
 783         /*
 784          * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
 785          * in write shadow mode. Checking DCWS before setting SPR 976.
 786          */
 787         if (mfspr(L1CSR2) & L1CSR2_DCWS)
 788                 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
 789 #endif
 790
 791 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
 792         spin = getenv("spin_table_compat");
 793         if (spin && (*spin == 'n'))
 794                 spin_table_compat = 0;
 795         else
 796                 spin_table_compat = 1;
 797 #endif
 798
 799         l2cache_init();
 800 #if defined(CONFIG_RAMBOOT_PBL)
 801         disable_cpc_sram();
 802 #endif
 803         enable_cpc();
 804 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
 805         enable_tdm_law();
 806 #endif
 807
 808 #ifndef CONFIG_SYS_FSL_NO_SERDES
 809         /* needs to be in ram since code uses global static vars */
 810         fsl_serdes_init();
 811 #endif
 812
 813 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 814 #define MCFGR_AXIPIPE 0x000000f0
 815         if (IS_SVR_REV(svr, 1, 0))
 816                 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
 817 #endif
 818
 819 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
 820         if (IS_SVR_REV(svr, 1, 0)) {
 821                 int i;
 822                 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
 823
 824                 for (i = 0; i < 12; i++) {
 825                         p += i + (i > 5 ? 11 : 0);
 826                         out_be32(p, 0x2);
 827                 }
 828                 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
 829                 out_be32(p, 0x34);
 830         }
 831 #endif
 832
 833 #ifdef CONFIG_SYS_SRIO
 834         srio_init();
 835 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 836         char *s = getenv("bootmaster");
 837         if (s) {
 838                 if (!strcmp(s, "SRIO1")) {
 839                         srio_boot_master(1);
 840                         srio_boot_master_release_slave(1);
 841                 }
 842                 if (!strcmp(s, "SRIO2")) {
 843                         srio_boot_master(2);
 844                         srio_boot_master_release_slave(2);
 845                 }
 846         }
 847 #endif
 848 #endif
 849
 850 #if defined(CONFIG_MP)
 851         setup_mp();
 852 #endif
 853
 854 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
 855         {
 856                 if (SVR_MAJ(svr) < 3) {
 857                         void *p;
 858                         p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
 859                         setbits_be32(p, 1 << (31 - 14));
 860                 }
 861         }
 862 #endif
 863
 864 #ifdef CONFIG_SYS_LBC_LCRR
 865         /*
 866          * Modify the CLKDIV field of LCRR register to improve the writing
 867          * speed for NOR flash.
 868          */
 869         clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
 870         __raw_readl(&lbc->lcrr);
 871         isync();
 872 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 873         udelay(100);
 874 #endif
 875 #endif
 876
 877 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 878         {
 879                 struct ccsr_usb_phy __iomem *usb_phy1 =
 880                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 881 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 882                 if (has_erratum_a006261())
 883                         fsl_erratum_a006261_workaround(usb_phy1);
 884 #endif
 885                 out_be32(&usb_phy1->usb_enable_override,
 886                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 887         }
 888 #endif
 889 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 890         {
 891                 struct ccsr_usb_phy __iomem *usb_phy2 =
 892                         (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
 893 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 894                 if (has_erratum_a006261())
 895                         fsl_erratum_a006261_workaround(usb_phy2);
 896 #endif
 897                 out_be32(&usb_phy2->usb_enable_override,
 898                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 899         }
 900 #endif
 901
 902 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
 903         /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
 904          * multi-bit ECC errors which has impact on performance, so software
 905          * should disable all ECC reporting from USB1 and USB2.
 906          */
 907         if (IS_SVR_REV(get_svr(), 1, 0)) {
 908                 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
 909                         (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
 910                 setbits_be32(&dcfg->ecccr1,
 911                                 (DCSR_DCFG_ECC_DISABLE_USB1 |
 912                                  DCSR_DCFG_ECC_DISABLE_USB2));
 913         }
 914 #endif
 915
 916 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
 917                 struct ccsr_usb_phy __iomem *usb_phy =
 918                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 919                 setbits_be32(&usb_phy->pllprg[1],
 920                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
 921                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
 922                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
 923                              CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
 924 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 925                 usb_single_source_clk_configure(usb_phy);
 926 #endif
 927                 setbits_be32(&usb_phy->port1.ctrl,
 928                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 929                 setbits_be32(&usb_phy->port1.drvvbuscfg,
 930                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 931                 setbits_be32(&usb_phy->port1.pwrfltcfg,
 932                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 933                 setbits_be32(&usb_phy->port2.ctrl,
 934                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 935                 setbits_be32(&usb_phy->port2.drvvbuscfg,
 936                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 937                 setbits_be32(&usb_phy->port2.pwrfltcfg,
 938                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 939
 940 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 941                 if (has_erratum_a006261())
 942                         fsl_erratum_a006261_workaround(usb_phy);
 943 #endif
 944
 945 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
 946
 947 #ifdef CONFIG_FMAN_ENET
 948         fman_enet_init();
 949 #endif
 950
 951 #ifdef CONFIG_FSL_CAAM
 952         sec_init();
 953 #endif
 954
 955 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
 956         /*
 957          * For P1022/1013 Rev1.0 silicon, after power on SATA host
 958          * controller is configured in legacy mode instead of the
 959          * expected enterprise mode. Software needs to clear bit[28]
 960          * of HControl register to change to enterprise mode from
 961          * legacy mode.  We assume that the controller is offline.
 962          */
 963         if (IS_SVR_REV(svr, 1, 0) &&
 964             ((SVR_SOC_VER(svr) == SVR_P1022) ||
 965              (SVR_SOC_VER(svr) == SVR_P1013))) {
 966                 fsl_sata_reg_t *reg;
 967
 968                 /* first SATA controller */
 969                 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
 970                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 971
 972                 /* second SATA controller */
 973                 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
 974                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 975         }
 976 #endif
 977
 978         init_used_tlb_cams();
 979
 980         return 0;
 981 }
 982
 983 void arch_preboot_os(void)
 984 {
 985         u32 msr;
 986
 987         /*
 988          * We are changing interrupt offsets and are about to boot the OS so
 989          * we need to make sure we disable all async interrupts. EE is already
 990          * disabled by the time we get called.
 991          */
 992         msr = mfmsr();
 993         msr &= ~(MSR_ME|MSR_CE);
 994         mtmsr(msr);
 995 }
 996
 997 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
 998 int sata_initialize(void)
 999 {
1000         if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
1001                 return __sata_initialize();
1002
1003         return 1;
1004 }
1005 #endif
1006
1007 void cpu_secondary_init_r(void)
1008 {
1009 #ifdef CONFIG_U_QE
1010         uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
1011 #elif defined CONFIG_QE
1012         uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
1013 #endif
1014
1015 #ifdef CONFIG_QE
1016         qe_init(qe_base);
1017         qe_reset();
1018 #endif
1019 }