arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  19                              unsigned int ctrl_num)
  20 {
  21         unsigned int i, bus_width;
  22         volatile ccsr_ddr_t *ddr;
  23         u32 temp_sdram_cfg;
  24         u32 total_gb_size_per_controller;
  25         int timeout;
  26 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  27         int timeout_save;
  28         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  29         unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  30         int csn = -1;
  31 #endif
  32
  33         switch (ctrl_num) {
  34         case 0:
  35                 ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
  36                 break;
  37 #if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  38         case 1:
  39                 ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
  40                 break;
  41 #endif
  42 #if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  43         case 2:
  44                 ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
  45                 break;
  46 #endif
  47 #if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  48         case 3:
  49                 ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
  50                 break;
  51 #endif
  52         default:
  53                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  54                 return;
  55         }
  56
  57         if (regs->ddr_eor)
  58                 out_be32(&ddr->eor, regs->ddr_eor);
  59 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  60         debug("Workaround for ERRATUM_DDR111_DDR134\n");
  61         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  62                 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  63                 cs_ea = regs->cs[i].bnds & 0xfff;
  64                 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  65                         csn = i;
  66                         csn_bnds_backup = regs->cs[i].bnds;
  67                         csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  68                         if (cs_ea > 0xeff)
  69                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  70                         else
  71                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  72                         debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  73                                 "change it to 0x%x\n",
  74                                 csn, csn_bnds_backup, regs->cs[i].bnds);
  75                         break;
  76                 }
  77         }
  78 #endif
  79         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  80                 if (i == 0) {
  81                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  82                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  83                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  84
  85                 } else if (i == 1) {
  86                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  87                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  88                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  89
  90                 } else if (i == 2) {
  91                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  92                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  93                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  94
  95                 } else if (i == 3) {
  96                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  97                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  98                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  99                 }
 100         }
 101
 102         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 103         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 104         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 105         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 106         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 107         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 108         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 109         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 110         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 111         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 112         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 113         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 114         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 115         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 116         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 117         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
 118         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 119         out_be32(&ddr->init_addr, regs->ddr_init_addr);
 120         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 121
 122         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 123         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 124         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 125         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 126 #ifndef CONFIG_SYS_FSL_DDR_EMU
 127         /*
 128          * Skip these two registers if running on emulator
 129          * because emulator doesn't have skew between bytes.
 130          */
 131
 132         if (regs->ddr_wrlvl_cntl_2)
 133                 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 134         if (regs->ddr_wrlvl_cntl_3)
 135                 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 136 #endif
 137
 138         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 139         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 140         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 141         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 142         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 143         out_be32(&ddr->err_disable, regs->err_disable);
 144         out_be32(&ddr->err_int_en, regs->err_int_en);
 145         for (i = 0; i < 32; i++) {
 146                 if (regs->debug[i]) {
 147                         debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
 148                         out_be32(&ddr->debug[i], regs->debug[i]);
 149                 }
 150         }
 151 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
 152         out_be32(&ddr->debug[28], 0x30003000);
 153 #endif
 154
 155 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 156         out_be32(&ddr->debug[12], 0x00000015);
 157         out_be32(&ddr->debug[21], 0x24000000);
 158 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 159
 160         /* Set, but do not enable the memory */
 161         temp_sdram_cfg = regs->ddr_sdram_cfg;
 162         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 163         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 164 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 165         debug("Workaround for ERRATUM_DDR_A003\n");
 166         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 167                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 168                 out_be32(&ddr->debug[2], 0x00000400);
 169                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 170                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 171                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 172                 out_be32(&ddr->mtcr, 0);
 173                 out_be32(&ddr->debug[12], 0x00000015);
 174                 out_be32(&ddr->debug[21], 0x24000000);
 175                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 176                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 177
 178                 asm volatile("sync;isync");
 179                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 180                         ;
 181
 182                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 183                 case 0x00000000:
 184                         out_be32(&ddr->sdram_md_cntl,
 185                                 MD_CNTL_MD_EN           |
 186                                 MD_CNTL_CS_SEL_CS0_CS1  |
 187                                 0x04000000              |
 188                                 MD_CNTL_WRCW            |
 189                                 MD_CNTL_MD_VALUE(0x02));
 190                         break;
 191                 case 0x00100000:
 192                         out_be32(&ddr->sdram_md_cntl,
 193                                 MD_CNTL_MD_EN           |
 194                                 MD_CNTL_CS_SEL_CS0_CS1  |
 195                                 0x04000000              |
 196                                 MD_CNTL_WRCW            |
 197                                 MD_CNTL_MD_VALUE(0x0a));
 198                         break;
 199                 case 0x00200000:
 200                         out_be32(&ddr->sdram_md_cntl,
 201                                 MD_CNTL_MD_EN           |
 202                                 MD_CNTL_CS_SEL_CS0_CS1  |
 203                                 0x04000000              |
 204                                 MD_CNTL_WRCW            |
 205                                 MD_CNTL_MD_VALUE(0x12));
 206                         break;
 207                 case 0x00300000:
 208                         out_be32(&ddr->sdram_md_cntl,
 209                                 MD_CNTL_MD_EN           |
 210                                 MD_CNTL_CS_SEL_CS0_CS1  |
 211                                 0x04000000              |
 212                                 MD_CNTL_WRCW            |
 213                                 MD_CNTL_MD_VALUE(0x1a));
 214                         break;
 215                 default:
 216                         out_be32(&ddr->sdram_md_cntl,
 217                                 MD_CNTL_MD_EN           |
 218                                 MD_CNTL_CS_SEL_CS0_CS1  |
 219                                 0x04000000              |
 220                                 MD_CNTL_WRCW            |
 221                                 MD_CNTL_MD_VALUE(0x02));
 222                         printf("Unsupported RC10\n");
 223                         break;
 224                 }
 225
 226                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 227                         ;
 228                 udelay(6);
 229                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 230                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 231                 out_be32(&ddr->debug[2], 0x0);
 232                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 233                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 234                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 235                 out_be32(&ddr->debug[12], 0x0);
 236                 out_be32(&ddr->debug[21], 0x0);
 237                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 238
 239         }
 240 #endif
 241         /*
 242          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 243          * when operatiing in 32-bit bus mode with 4-beat bursts,
 244          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 245          */
 246 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 247         debug("Workaround for ERRATUM_DDR_115\n");
 248         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 249             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 250                 /* set DEBUG_1[31] */
 251                 setbits_be32(&ddr->debug[0], 1);
 252         }
 253 #endif
 254 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 255         debug("Workaround for ERRATUM_DDR111_DDR134\n");
 256         /*
 257          * This is the combined workaround for DDR111 and DDR134
 258          * following the published errata for MPC8572
 259          */
 260
 261         /* 1. Set EEBACR[3] */
 262         setbits_be32(&ecm->eebacr, 0x10000000);
 263         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 264
 265         /* 2. Set DINIT in SDRAM_CFG_2*/
 266         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 267         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 268                 in_be32(&ddr->sdram_cfg_2));
 269
 270         /* 3. Set DEBUG_3[21] */
 271         setbits_be32(&ddr->debug[2], 0x400);
 272         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 273
 274 #endif  /* part 1 of the workaound */
 275
 276         /*
 277          * 500 painful micro-seconds must elapse between
 278          * the DDR clock setup and the DDR config enable.
 279          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 280          * we choose the max, that is 500 us for all of case.
 281          */
 282         udelay(500);
 283         asm volatile("sync;isync");
 284
 285         /* Let the controller go */
 286         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 287         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 288         asm volatile("sync;isync");
 289
 290         total_gb_size_per_controller = 0;
 291         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 292                 if (!(regs->cs[i].config & 0x80000000))
 293                         continue;
 294                 total_gb_size_per_controller += 1 << (
 295                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 296                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 297                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 298                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 299                         26);                    /* minus 26 (count of 64M) */
 300         }
 301         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 302                 total_gb_size_per_controller *= 3;
 303         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 304                 total_gb_size_per_controller <<= 1;
 305         /*
 306          * total memory / bus width = transactions needed
 307          * transactions needed / data rate = seconds
 308          * to add plenty of buffer, double the time
 309          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 310          * Let's wait for 800ms
 311          */
 312         bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
 313                         >> SDRAM_CFG_DBW_SHIFT);
 314         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 315                 (get_ddr_freq(0) >> 20)) << 1;
 316 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 317         timeout_save = timeout;
 318 #endif
 319         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 320         debug("total %d GB\n", total_gb_size_per_controller);
 321         debug("Need to wait up to %d * 10ms\n", timeout);
 322
 323         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 324         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 325                 (timeout >= 0)) {
 326                 udelay(10000);          /* throttle polling rate */
 327                 timeout--;
 328         }
 329
 330         if (timeout <= 0)
 331                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 332
 333 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 334         /* continue this workaround */
 335
 336         /* 4. Clear DEBUG3[21] */
 337         clrbits_be32(&ddr->debug[2], 0x400);
 338         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 339
 340         /* DDR134 workaround starts */
 341         /* A: Clear sdram_cfg_2[odt_cfg] */
 342         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 343         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 344                 in_be32(&ddr->sdram_cfg_2));
 345
 346         /* B: Set DEBUG1[15] */
 347         setbits_be32(&ddr->debug[0], 0x10000);
 348         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 349
 350         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 351         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 352         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 353                 in_be32(&ddr->timing_cfg_2));
 354
 355         /* D: Set D6 to 0x9f9f9f9f */
 356         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 357         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 358
 359         /* E: Set D7 to 0x9f9f9f9f */
 360         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 361         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 362
 363         /* F: Set D2[20] */
 364         setbits_be32(&ddr->debug[1], 0x800);
 365         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 366
 367         /* G: Poll on D2[20] until cleared */
 368         while (in_be32(&ddr->debug[1]) & 0x800)
 369                 udelay(10000);          /* throttle polling rate */
 370
 371         /* H: Clear D1[15] */
 372         clrbits_be32(&ddr->debug[0], 0x10000);
 373         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 374
 375         /* I: Set sdram_cfg_2[odt_cfg] */
 376         setbits_be32(&ddr->sdram_cfg_2,
 377                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 378         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 379
 380         /* Continuing with the DDR111 workaround */
 381         /* 5. Set D2[21] */
 382         setbits_be32(&ddr->debug[1], 0x400);
 383         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 384
 385         /* 6. Poll D2[21] until its cleared */
 386         while (in_be32(&ddr->debug[1]) & 0x400)
 387                 udelay(10000);          /* throttle polling rate */
 388
 389         /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
 390         debug("Wait for %d * 10ms\n", timeout_save);
 391         udelay(timeout_save * 10000);
 392
 393         /* 8. Set sdram_cfg_2[dinit] if options requires */
 394         setbits_be32(&ddr->sdram_cfg_2,
 395                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 396         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 397
 398         /* 9. Poll until dinit is cleared */
 399         timeout = timeout_save;
 400         debug("Need to wait up to %d * 10ms\n", timeout);
 401         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 402                 (timeout >= 0)) {
 403                 udelay(10000);          /* throttle polling rate */
 404                 timeout--;
 405         }
 406
 407         if (timeout <= 0)
 408                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 409
 410         /* 10. Clear EEBACR[3] */
 411         clrbits_be32(&ecm->eebacr, 10000000);
 412         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 413
 414         if (csn != -1) {
 415                 csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
 416                 *csn_bnds_t = csn_bnds_backup;
 417                 debug("Change cs%d_bnds back to 0x%08x\n",
 418                         csn, regs->cs[csn].bnds);
 419                 setbits_be32(&ddr->sdram_cfg, 0x2);     /* MEM_HALT */
 420                 switch (csn) {
 421                 case 0:
 422                         out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
 423                         break;
 424                 case 1:
 425                         out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 426                         break;
 427                 case 2:
 428                         out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 429                         break;
 430                 case 3:
 431                         out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 432                         break;
 433                 }
 434                 clrbits_be32(&ddr->sdram_cfg, 0x2);
 435         }
 436 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 437 }