arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  19                              unsigned int ctrl_num)
  20 {
  21         unsigned int i;
  22         volatile ccsr_ddr_t *ddr;
  23         u32 temp_sdram_cfg;
  24 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  25         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  26         u32 total_gb_size_per_controller;
  27 #endif
  28
  29         switch (ctrl_num) {
  30         case 0:
  31                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  32                 break;
  33         case 1:
  34                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
  35                 break;
  36         default:
  37                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  38                 return;
  39         }
  40
  41         out_be32(&ddr->eor, regs->ddr_eor);
  42
  43         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  44                 if (i == 0) {
  45                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  46                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  47                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  48
  49                 } else if (i == 1) {
  50                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  51                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  52                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  53
  54                 } else if (i == 2) {
  55                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  56                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  57                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  58
  59                 } else if (i == 3) {
  60                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  61                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  62                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  63                 }
  64         }
  65
  66         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  67         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  68         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  69         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  70         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  71         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  72         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  73         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
  74         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
  75         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
  76         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
  77         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
  78         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
  79         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  80         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  81         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
  82         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  83         out_be32(&ddr->init_addr, regs->ddr_init_addr);
  84         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
  85
  86         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
  87         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
  88         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
  89         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
  90         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
  91         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
  92         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
  93         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
  94         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
  95         out_be32(&ddr->err_disable, regs->err_disable);
  96         out_be32(&ddr->err_int_en, regs->err_int_en);
  97         for (i = 0; i < 32; i++)
  98                 out_be32(&ddr->debug[i], regs->debug[i]);
  99
 100         /* Set, but do not enable the memory */
 101         temp_sdram_cfg = regs->ddr_sdram_cfg;
 102         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 103         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 104 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 105         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 106                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 107                 out_be32(&ddr->debug[2], 0x00000400);
 108                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 109                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 110                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 111                 out_be32(&ddr->mtcr, 0);
 112                 out_be32(&ddr->debug[12], 0x00000015);
 113                 out_be32(&ddr->debug[21], 0x24000000);
 114                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 115                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 116
 117                 asm volatile("sync;isync");
 118                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 119                         ;
 120
 121                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 122                 case 0x00000000:
 123                         out_be32(&ddr->sdram_md_cntl,
 124                                 MD_CNTL_MD_EN           |
 125                                 MD_CNTL_CS_SEL_CS0_CS1  |
 126                                 0x04000000              |
 127                                 MD_CNTL_WRCW            |
 128                                 MD_CNTL_MD_VALUE(0x02));
 129                         break;
 130                 case 0x00100000:
 131                         out_be32(&ddr->sdram_md_cntl,
 132                                 MD_CNTL_MD_EN           |
 133                                 MD_CNTL_CS_SEL_CS0_CS1  |
 134                                 0x04000000              |
 135                                 MD_CNTL_WRCW            |
 136                                 MD_CNTL_MD_VALUE(0x0a));
 137                         break;
 138                 case 0x00200000:
 139                         out_be32(&ddr->sdram_md_cntl,
 140                                 MD_CNTL_MD_EN           |
 141                                 MD_CNTL_CS_SEL_CS0_CS1  |
 142                                 0x04000000              |
 143                                 MD_CNTL_WRCW            |
 144                                 MD_CNTL_MD_VALUE(0x12));
 145                         break;
 146                 case 0x00300000:
 147                         out_be32(&ddr->sdram_md_cntl,
 148                                 MD_CNTL_MD_EN           |
 149                                 MD_CNTL_CS_SEL_CS0_CS1  |
 150                                 0x04000000              |
 151                                 MD_CNTL_WRCW            |
 152                                 MD_CNTL_MD_VALUE(0x1a));
 153                         break;
 154                 default:
 155                         out_be32(&ddr->sdram_md_cntl,
 156                                 MD_CNTL_MD_EN           |
 157                                 MD_CNTL_CS_SEL_CS0_CS1  |
 158                                 0x04000000              |
 159                                 MD_CNTL_WRCW            |
 160                                 MD_CNTL_MD_VALUE(0x02));
 161                         printf("Unsupported RC10\n");
 162                         break;
 163                 }
 164
 165                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 166                         ;
 167                 udelay(6);
 168                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 169                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 170                 out_be32(&ddr->debug[2], 0x0);
 171                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 172                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 173                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 174                 out_be32(&ddr->debug[12], 0x0);
 175                 out_be32(&ddr->debug[21], 0x0);
 176                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 177
 178         }
 179 #endif
 180         /*
 181          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 182          * when operatiing in 32-bit bus mode with 4-beat bursts,
 183          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 184          */
 185 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 186         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 187             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 188                 /* set DEBUG_1[31] */
 189                 setbits_be32(&ddr->debug[0], 1);
 190         }
 191 #endif
 192 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 193         /*
 194          * This is the combined workaround for DDR111 and DDR134
 195          * following the published errata for MPC8572
 196          */
 197
 198         /* 1. Set EEBACR[3] */
 199         setbits_be32(&ecm->eebacr, 0x10000000);
 200         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 201
 202         /* 2. Set DINIT in SDRAM_CFG_2*/
 203         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 204         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 205                 in_be32(&ddr->sdram_cfg_2));
 206
 207         /* 3. Set DEBUG_3[21] */
 208         setbits_be32(&ddr->debug[2], 0x400);
 209         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 210
 211 #endif  /* part 1 of the workaound */
 212
 213         /*
 214          * 500 painful micro-seconds must elapse between
 215          * the DDR clock setup and the DDR config enable.
 216          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 217          * we choose the max, that is 500 us for all of case.
 218          */
 219         udelay(500);
 220         asm volatile("sync;isync");
 221
 222         /* Let the controller go */
 223         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 224         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 225         asm volatile("sync;isync");
 226
 227         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 228         while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
 229                 udelay(10000);          /* throttle polling rate */
 230
 231 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 232         /* continue this workaround */
 233
 234         /* 4. Clear DEBUG3[21] */
 235         clrbits_be32(&ddr->debug[2], 0x400);
 236         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 237
 238         /* DDR134 workaround starts */
 239         /* A: Clear sdram_cfg_2[odt_cfg] */
 240         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 241         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 242                 in_be32(&ddr->sdram_cfg_2));
 243
 244         /* B: Set DEBUG1[15] */
 245         setbits_be32(&ddr->debug[0], 0x10000);
 246         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 247
 248         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 249         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 250         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 251                 in_be32(&ddr->timing_cfg_2));
 252
 253         /* D: Set D6 to 0x9f9f9f9f */
 254         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 255         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 256
 257         /* E: Set D7 to 0x9f9f9f9f */
 258         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 259         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 260
 261         /* F: Set D2[20] */
 262         setbits_be32(&ddr->debug[1], 0x800);
 263         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 264
 265         /* G: Poll on D2[20] until cleared */
 266         while (in_be32(&ddr->debug[1]) & 0x800)
 267                 udelay(10000);          /* throttle polling rate */
 268
 269         /* H: Clear D1[15] */
 270         clrbits_be32(&ddr->debug[0], 0x10000);
 271         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 272
 273         /* I: Set sdram_cfg_2[odt_cfg] */
 274         setbits_be32(&ddr->sdram_cfg_2,
 275                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 276         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 277
 278         /* Continuing with the DDR111 workaround */
 279         /* 5. Set D2[21] */
 280         setbits_be32(&ddr->debug[1], 0x400);
 281         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 282
 283         /* 6. Poll D2[21] until its cleared */
 284         while (in_be32(&ddr->debug[1]) & 0x400)
 285                 udelay(10000);          /* throttle polling rate */
 286
 287         /* 7. Wait for 400ms/GB */
 288         total_gb_size_per_controller = 0;
 289         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 290                 total_gb_size_per_controller +=
 291                                 ((regs->cs[i].bnds & 0xFFFF) >> 6)
 292                                 - (regs->cs[i].bnds >> 22) + 1;
 293         }
 294         if (in_be32(&ddr->sdram_cfg) & 0x80000)
 295                 total_gb_size_per_controller <<= 1;
 296         debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
 297         udelay(total_gb_size_per_controller * 400000);
 298
 299         /* 8. Set sdram_cfg_2[dinit] if options requires */
 300         setbits_be32(&ddr->sdram_cfg_2,
 301                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 302         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 303
 304         /* 9. Poll until dinit is cleared */
 305         while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
 306                 udelay(10000);
 307
 308         /* 10. Clear EEBACR[3] */
 309         clrbits_be32(&ecm->eebacr, 10000000);
 310         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 311 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 312 }