arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  19                              unsigned int ctrl_num)
  20 {
  21         unsigned int i, bus_width;
  22         volatile ccsr_ddr_t *ddr;
  23         u32 temp_sdram_cfg;
  24         u32 total_gb_size_per_controller;
  25         int timeout, timeout_save;
  26 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  27         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  28         unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  29         int csn = -1;
  30 #endif
  31
  32         switch (ctrl_num) {
  33         case 0:
  34                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  35                 break;
  36 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  37         case 1:
  38                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
  39                 break;
  40 #endif
  41 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  42         case 2:
  43                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
  44                 break;
  45 #endif
  46 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  47         case 3:
  48                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
  49                 break;
  50 #endif
  51         default:
  52                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  53                 return;
  54         }
  55
  56         if (regs->ddr_eor)
  57                 out_be32(&ddr->eor, regs->ddr_eor);
  58 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  59         debug("Workaround for ERRATUM_DDR111_DDR134\n");
  60         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  61                 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  62                 cs_ea = regs->cs[i].bnds & 0xfff;
  63                 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  64                         csn = i;
  65                         csn_bnds_backup = regs->cs[i].bnds;
  66                         csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  67                         if (cs_ea > 0xeff)
  68                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  69                         else
  70                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  71                         debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  72                                 "change it to 0x%x\n",
  73                                 csn, csn_bnds_backup, regs->cs[i].bnds);
  74                         break;
  75                 }
  76         }
  77 #endif
  78         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  79                 if (i == 0) {
  80                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  81                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  82                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  83
  84                 } else if (i == 1) {
  85                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  86                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  87                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  88
  89                 } else if (i == 2) {
  90                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  91                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  92                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  93
  94                 } else if (i == 3) {
  95                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  96                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  97                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  98                 }
  99         }
 100
 101         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 102         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 103         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 104         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 105         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 106         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 107         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 108         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 109         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 110         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 111         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 112         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 113         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 114         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 115         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 116         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
 117         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 118         out_be32(&ddr->init_addr, regs->ddr_init_addr);
 119         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 120
 121         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 122         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 123         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 124         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 125         if (regs->ddr_wrlvl_cntl_2)
 126                 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 127         if (regs->ddr_wrlvl_cntl_3)
 128                 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 129
 130         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 131         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 132         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 133         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 134         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 135         out_be32(&ddr->err_disable, regs->err_disable);
 136         out_be32(&ddr->err_int_en, regs->err_int_en);
 137         for (i = 0; i < 32; i++) {
 138                 if (regs->debug[i]) {
 139                         debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
 140                         out_be32(&ddr->debug[i], regs->debug[i]);
 141                 }
 142         }
 143
 144 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 145         out_be32(&ddr->debug[12], 0x00000015);
 146         out_be32(&ddr->debug[21], 0x24000000);
 147 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 148
 149         /* Set, but do not enable the memory */
 150         temp_sdram_cfg = regs->ddr_sdram_cfg;
 151         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 152         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 153 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 154         debug("Workaround for ERRATUM_DDR_A003\n");
 155         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 156                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 157                 out_be32(&ddr->debug[2], 0x00000400);
 158                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 159                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 160                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 161                 out_be32(&ddr->mtcr, 0);
 162                 out_be32(&ddr->debug[12], 0x00000015);
 163                 out_be32(&ddr->debug[21], 0x24000000);
 164                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 165                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 166
 167                 asm volatile("sync;isync");
 168                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 169                         ;
 170
 171                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 172                 case 0x00000000:
 173                         out_be32(&ddr->sdram_md_cntl,
 174                                 MD_CNTL_MD_EN           |
 175                                 MD_CNTL_CS_SEL_CS0_CS1  |
 176                                 0x04000000              |
 177                                 MD_CNTL_WRCW            |
 178                                 MD_CNTL_MD_VALUE(0x02));
 179                         break;
 180                 case 0x00100000:
 181                         out_be32(&ddr->sdram_md_cntl,
 182                                 MD_CNTL_MD_EN           |
 183                                 MD_CNTL_CS_SEL_CS0_CS1  |
 184                                 0x04000000              |
 185                                 MD_CNTL_WRCW            |
 186                                 MD_CNTL_MD_VALUE(0x0a));
 187                         break;
 188                 case 0x00200000:
 189                         out_be32(&ddr->sdram_md_cntl,
 190                                 MD_CNTL_MD_EN           |
 191                                 MD_CNTL_CS_SEL_CS0_CS1  |
 192                                 0x04000000              |
 193                                 MD_CNTL_WRCW            |
 194                                 MD_CNTL_MD_VALUE(0x12));
 195                         break;
 196                 case 0x00300000:
 197                         out_be32(&ddr->sdram_md_cntl,
 198                                 MD_CNTL_MD_EN           |
 199                                 MD_CNTL_CS_SEL_CS0_CS1  |
 200                                 0x04000000              |
 201                                 MD_CNTL_WRCW            |
 202                                 MD_CNTL_MD_VALUE(0x1a));
 203                         break;
 204                 default:
 205                         out_be32(&ddr->sdram_md_cntl,
 206                                 MD_CNTL_MD_EN           |
 207                                 MD_CNTL_CS_SEL_CS0_CS1  |
 208                                 0x04000000              |
 209                                 MD_CNTL_WRCW            |
 210                                 MD_CNTL_MD_VALUE(0x02));
 211                         printf("Unsupported RC10\n");
 212                         break;
 213                 }
 214
 215                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 216                         ;
 217                 udelay(6);
 218                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 219                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 220                 out_be32(&ddr->debug[2], 0x0);
 221                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 222                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 223                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 224                 out_be32(&ddr->debug[12], 0x0);
 225                 out_be32(&ddr->debug[21], 0x0);
 226                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 227
 228         }
 229 #endif
 230         /*
 231          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 232          * when operatiing in 32-bit bus mode with 4-beat bursts,
 233          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 234          */
 235 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 236         debug("Workaround for ERRATUM_DDR_115\n");
 237         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 238             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 239                 /* set DEBUG_1[31] */
 240                 setbits_be32(&ddr->debug[0], 1);
 241         }
 242 #endif
 243 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 244         debug("Workaround for ERRATUM_DDR111_DDR134\n");
 245         /*
 246          * This is the combined workaround for DDR111 and DDR134
 247          * following the published errata for MPC8572
 248          */
 249
 250         /* 1. Set EEBACR[3] */
 251         setbits_be32(&ecm->eebacr, 0x10000000);
 252         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 253
 254         /* 2. Set DINIT in SDRAM_CFG_2*/
 255         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 256         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 257                 in_be32(&ddr->sdram_cfg_2));
 258
 259         /* 3. Set DEBUG_3[21] */
 260         setbits_be32(&ddr->debug[2], 0x400);
 261         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 262
 263 #endif  /* part 1 of the workaound */
 264
 265         /*
 266          * 500 painful micro-seconds must elapse between
 267          * the DDR clock setup and the DDR config enable.
 268          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 269          * we choose the max, that is 500 us for all of case.
 270          */
 271         udelay(500);
 272         asm volatile("sync;isync");
 273
 274         /* Let the controller go */
 275         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 276         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 277         asm volatile("sync;isync");
 278
 279         total_gb_size_per_controller = 0;
 280         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 281                 if (!(regs->cs[i].config & 0x80000000))
 282                         continue;
 283                 total_gb_size_per_controller += 1 << (
 284                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 285                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 286                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 287                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 288                         26);                    /* minus 26 (count of 64M) */
 289         }
 290         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 291                 total_gb_size_per_controller *= 3;
 292         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 293                 total_gb_size_per_controller <<= 1;
 294         /*
 295          * total memory / bus width = transactions needed
 296          * transactions needed / data rate = seconds
 297          * to add plenty of buffer, double the time
 298          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 299          * Let's wait for 800ms
 300          */
 301         bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
 302                         >> SDRAM_CFG_DBW_SHIFT);
 303         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 304                 (get_ddr_freq(0) >> 20)) << 1;
 305         timeout_save = timeout;
 306         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 307         debug("total %d GB\n", total_gb_size_per_controller);
 308         debug("Need to wait up to %d * 10ms\n", timeout);
 309
 310         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 311         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 312                 (timeout >= 0)) {
 313                 udelay(10000);          /* throttle polling rate */
 314                 timeout--;
 315         }
 316
 317         if (timeout <= 0)
 318                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 319
 320 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 321         /* continue this workaround */
 322
 323         /* 4. Clear DEBUG3[21] */
 324         clrbits_be32(&ddr->debug[2], 0x400);
 325         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 326
 327         /* DDR134 workaround starts */
 328         /* A: Clear sdram_cfg_2[odt_cfg] */
 329         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 330         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 331                 in_be32(&ddr->sdram_cfg_2));
 332
 333         /* B: Set DEBUG1[15] */
 334         setbits_be32(&ddr->debug[0], 0x10000);
 335         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 336
 337         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 338         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 339         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 340                 in_be32(&ddr->timing_cfg_2));
 341
 342         /* D: Set D6 to 0x9f9f9f9f */
 343         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 344         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 345
 346         /* E: Set D7 to 0x9f9f9f9f */
 347         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 348         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 349
 350         /* F: Set D2[20] */
 351         setbits_be32(&ddr->debug[1], 0x800);
 352         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 353
 354         /* G: Poll on D2[20] until cleared */
 355         while (in_be32(&ddr->debug[1]) & 0x800)
 356                 udelay(10000);          /* throttle polling rate */
 357
 358         /* H: Clear D1[15] */
 359         clrbits_be32(&ddr->debug[0], 0x10000);
 360         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 361
 362         /* I: Set sdram_cfg_2[odt_cfg] */
 363         setbits_be32(&ddr->sdram_cfg_2,
 364                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 365         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 366
 367         /* Continuing with the DDR111 workaround */
 368         /* 5. Set D2[21] */
 369         setbits_be32(&ddr->debug[1], 0x400);
 370         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 371
 372         /* 6. Poll D2[21] until its cleared */
 373         while (in_be32(&ddr->debug[1]) & 0x400)
 374                 udelay(10000);          /* throttle polling rate */
 375
 376         /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
 377         debug("Wait for %d * 10ms\n", timeout_save);
 378         udelay(timeout_save * 10000);
 379
 380         /* 8. Set sdram_cfg_2[dinit] if options requires */
 381         setbits_be32(&ddr->sdram_cfg_2,
 382                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 383         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 384
 385         /* 9. Poll until dinit is cleared */
 386         timeout = timeout_save;
 387         debug("Need to wait up to %d * 10ms\n", timeout);
 388         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 389                 (timeout >= 0)) {
 390                 udelay(10000);          /* throttle polling rate */
 391                 timeout--;
 392         }
 393
 394         if (timeout <= 0)
 395                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 396
 397         /* 10. Clear EEBACR[3] */
 398         clrbits_be32(&ecm->eebacr, 10000000);
 399         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 400
 401         if (csn != -1) {
 402                 csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
 403                 *csn_bnds_t = csn_bnds_backup;
 404                 debug("Change cs%d_bnds back to 0x%08x\n",
 405                         csn, regs->cs[csn].bnds);
 406                 setbits_be32(&ddr->sdram_cfg, 0x2);     /* MEM_HALT */
 407                 switch (csn) {
 408                 case 0:
 409                         out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
 410                         break;
 411                 case 1:
 412                         out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 413                         break;
 414                 case 2:
 415                         out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 416                         break;
 417                 case 3:
 418                         out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 419                         break;
 420                 }
 421                 clrbits_be32(&ddr->sdram_cfg, 0x2);
 422         }
 423 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 424 }